WM8351 datasheet(198/330 Pages) WOLFSON

198 / 330 page

WM8351

Production Data

PD, April 2012, Rev 4.5

198

24 INTERRUPT CONTROLLER

The WM8351 can send an interrupt signal to the host processor though the IRQ pin. Interrupts can

alert the host to a wide range of events and fault conditions. Each of these can be individually

enabled or masked. After receiving an interrupt, the host processor can read the interrupt registers in

order to determine what caused the interrupt, and take appropriate action if required.

The WM8351 interrupt controller has two levels:

Second-level interrupts indicate a single event in one of the circuit blocks. This is indicated by setting

a register bit. This bit is a “sticky” bit - once it is set, it remains at logic 1 until the host processor reads

the register. When the processor reads the register, the interrupt bits in that register are cleared. First-

level interrupts are the logical OR of several second-level interrupts (usually all the interrupts

associated with one particular circuit block). The default polarity of IRQ is active low, meaning that the

IRQ signal is the logical NOR of all first-level interrupts.

Individual second-level interrupt bits can be masked, which prevents them from setting the First-level

interrupt. (Note that the “sticky” bit will be set as normal, even if that interrupt is masked.)

Individual first-level interrupts can also be masked, preventing them from asserting the IRQ output.

Figure 80 Interrupt Equivalent Logic

To find the cause of an interrupt signal, the host processor should first read the first-level interrupt

cause(s) of the interrupt can be determined by reading the second-level interrupt register(s) as

appropriate to the indicated first-level interrupt event.

WM8351 Datasheet(PDF) 198 Page - Wolfson Microelectronics plc