WM8351 datasheet(200/330 Pages) WOLFSON

200 / 330 page

WM8351

Production Data

PD, April 2012, Rev 4.5

200

24.3 SECOND-LEVEL INTERRUPTS

The following sections define the second-level interrupt status and control bits associated with each of

the first-level bits defined in Table 142.

24.3.1

OVERCURRENT INTERRUPTS

The first-level OC_INT interrupt comprises one second-level interrupt for the limit switch. This status

bit is in Register R29 and its mask bit is in Register R37, as defined in Table 143.

ADDRESS

BIT

LABEL

DESCRIPTION

R29 (1Dh)

Over Current

Interrupt Status

OC_LS_EINT

Limit Switch Over-current interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

R37 (25h)

Over Current

Interrupt Mask

IM_OC_LS_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

When IM_OC_LS_EINT is set to 1, then

OC_LS_EINT in R29 does not trigger an

OC_INT interrupt when set. The default

value is 0 (unmasked).

Table 143 Over-Current Interrupts

24.3.2

UNDERVOLTAGE INTERRUPTS

The first-level UV_INT interrupt comprises several second-level interrupts for the DC-DCs and LDOs.

Each of these has a status bit in Register R28 and a mask bit in Register R36, as defined in Table

144.

ADDRESS

BIT

LABEL

DESCRIPTION

R28 (1Ch)

Under Voltage

Interrupt Status

UV_LDO4_EINT

LDO4 Under-voltage interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

UV_LDO3_EINT

LDO3 Under-voltage interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

UV_LDO2_EINT

LDO2 Under-voltage interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

UV_LDO1_EINT

LDO1 Under-voltage interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

UV_DC4_EINT

DCDC4 Under-voltage interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

UV_DC3_EINT

DCDC3 Under-voltage interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

UV_DC2_EINT

DCDC2 Under-voltage interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

UV_DC1_EINT

DCDC1 Under-voltage interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

R36 (24h)

Under Voltage

Interrupt Mask

11:0

“IM_” + name of respective bit

in R28

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Each bit in R36 enables or masks the

corresponding bit in R28. The default

value for these bits is 0 (unmasked).

Table 144 Under Voltage Interrupts

WM8351 Datasheet(PDF) 200 Page - Wolfson Microelectronics plc

WM8351 Datasheet(HTML) 200 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL