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WM8351 Datasheet(PDF) 199 Page - Wolfson Microelectronics plc |
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WM8351 Datasheet(HTML) 199 Page - Wolfson Microelectronics plc |
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199 / 330 page  Production Data WM8351 w PD, April 2012, Rev 4.5 199 24.1 CONFIGURING THE IRQ PIN The default polarity of IRQ is active low; this can be changed to active high if desired, by writing to the IRQ_POL bit. When the WM8351 is in the HIBERNATE state, interrupts can be disabled or can remain active. The desired behaviour can be selected using the IRQ_HIB_MODE bit. ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 (03h) System Control 1 0 IRQ_POL 0 IRQ pin polarity 0 = active low (/IRQ) 1 = active high (IRQ) R5 (05h) System Hibernate 3 IRQ_HIB_MOD E 0 IRQ pin state in hibernate mode 0 = Normal operation 1 = Forced to indicate there is no IRQ. Table 141 Interrupts in HIBERNATE State 24.2 FIRST LEVEL INTERRUPTS Each first level interrupt has a status bit in Register R24, which can be read to determine the origin of an IRQ event. Each of these bits may be masked by setting the corresponding field in Register R32. ADDRESS BIT LABEL DESCRIPTION R24 (18h) System Interrupts 13 OC_INT First-level over-current interrupt. Note: This bit is cleared once read. 12 UV_INT First-level under-voltage interrupt. Note: This bit is cleared once read. 9 CS_INT First-level current sink interrupt. Note: This bit is cleared once read. 8 EXT_INT First-level external interrupt. Note: This bit is cleared once read. 7 CODEC_INT First-level codec interrupt. Note: This bit is cleared once read. 6 GP_INT First-level GPIO interrupt. Note: This bit is cleared once read. 5 AUXADC_INT First-level AUXADC comparator interrupt. Note: This bit is cleared once read. 4 RTC_INT First-level RTC interrupt. Note: This bit is cleared once read. 3 SYS_INT First-level system interrupt. Note: This bit is cleared once read. 2 CHG_INT First-level charger interrupt. Note: This bit is cleared once read. 1 USB_INT First-level USB interrupt. Note: This bit is cleared once read. 0 WKUP_INT First-level wakeup interrupt. Note: This bit is cleared once read. R32 (20h) System Interrupt Mask 13:0 “IM_” + name of respective bit in R25 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Each bit in R32 enables or masks the corresponding bit in R24. The default value for these bits is 1 (masked) Note: Register is R24 is read-only. Table 142 First Level Interrupt Status and Mask Bits |
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