WM8351 datasheet(201/330 Pages) WOLFSON

201 / 330 page

Production Data

WM8351

PD, April 2012, Rev 4.5

201

24.3.3

CURRENT SINK (LED DRIVER) INTERRUPTS

The first-level CS_INT interrupt comprises one second-level interrupt for the Current Sink functions.

This status bit is in Register R26 and its mask bit is in Register R34, as defined in Table 145.

ADDRESS

BIT

LABEL

DESCRIPTION

R26 (1Ah)

Interrupt Status

CS1_EINT

Flag to indicate drain voltage can no

longer be regulated and output current

may be out of spec.

(Rising Edge triggered)

Note: This bit is cleared once read.

R34 (22h)

Interrupt Status

2 Mask

IM_CS1_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

When IM_CS1_EINT is set to 1, then

CS1_EINT in R26 does not trigger a

CS_INT interrupt when set. The default

value is 0 (unmasked).

Table 145 Current Sink Interrupts

24.3.4

EXTERNAL INTERRUPTS

The first-level EXT_INT interrupt comprises three second-level interrupts for USB, Wall and Battery

supply status. Each of these has a status bit in Register R31 and a mask bit in Register R37, as

defined in Table 146. These flags are triggered on the rising and falling edges of the interrupt events.

ADDRESS

BIT

LABEL

DESCRIPTION

R31 (1Fh)

Comparator

Interrupt Status

EXT_USB_FB_EINT

USB_FB changed interrupt.

(Rising and Falling Edge triggered)

Note: This bit is cleared once read.

EXT_WALL_FB_EINT

WALL_FB changed interrupt.

(Rising and Falling Edge triggered)

Note: This bit is cleared once read.

EXT_BATT_FB_EINT

BATT_FB changed interrupt.

(Rising and Falling Edge triggered)

Note: This bit is cleared once read.

R39 (27h)

Comparator

Interrupt Status

Mask

15:13

“IM_” + name of respective bit

in R31

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Each bit in R39 enables or masks the

corresponding bit in R31. The default

value for these bits is 0 (unmasked).

Table 146 External Interrupts

24.3.5

CODEC INTERRUPTS

The first-level CODEC_INT interrupt comprises four second-level interrupts for the CODEC. Each of

these has a status bit in Register R31 and a mask bit in Register R39, as defined in Table 147. These

flags are triggered on the rising and falling edges of the interrupt events.

WM8351 Datasheet(PDF) 201 Page - Wolfson Microelectronics plc

WM8351 Datasheet(HTML) 201 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL