ADV7192 datasheet(6/69 Pages) AD

6 / 69 page

ADV7192

–6–

REV. 0

5 V TIMING CHARACTERISTICS

Parameter

Min

Typ

Max

Unit

Test Conditions

MPU PORT

SCLOCK Frequency

400

kHz

SCLOCK High Pulsewidth, t1

0.6

µs

SCLOCK Low Pulsewidth, t2

1.3

µs

Hold Time (Start Condition), t3

0.6

µs

After This Period the First Clock Is Generated

Setup Time (Start Condition), t4

0.6

µs

Relevant for Repeated Start Condition

Data Setup Time, t5

100

SDATA, SCLOCK Rise Time, t6

300

SDATA, SCLOCK Fall Time, t7

300

Setup Time (Stop Condition), t8

0.6

µs

ANALOG OUTPUTS2

Analog Output Delay

DAC Analog Output Skew

0.1

CLOCK CONTROL AND PIXEL

PORT

fCLOCK

MHz

Clock High Time, t9

Clock Low Time, t10

Data Setup Time, t11

2.5

Data Hold Time, t12

2.0

Control Setup Time, t11

6ns

Control Hold Time, t12

4ns

Digital Output Access Time, t13

Digital Output Hold Time, t14

Pipeline Delay, t15 (2

× Oversampling)

Clock Cycles

Pipeline Delay, t15 (4

× Oversampling)

Clock Cycles

TELETEXT PORT

Digital Output Access Time, t16

Data Setup Time, t17

3ns

Data Hold Time, t18

6ns

RESET CONTROL

RESET Low Time

PLL

PLL Output Frequency

MHz

NOTES

1Temperature range T

MIN to TMAX: 0

°C to 70°C.

2Guaranteed by characterization.

3Pixel Port consists of:

Data: P7–P0, Y0/P8–Y7/P15 Pixel Inputs

Control: HSYNC, VSYNC, BLANK

Clock: CLKIN

4Teletext Port consists of:

Digital Output: TTXRQ

Data: TTX

Speciﬁcations subject to change without notice.

(VAA = 5 V

250 mV, VREF = 1.235 V, RSET1,2 = 1200 V unless otherwise noted. All

speciﬁcations TMIN to TMAX

1 unless otherwise noted.)

ADV7192 Datasheet(PDF) 6 Page - Analog Devices

ADV7192 Datasheet(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Datasheet Download

Link URL