ADV7192 datasheet(30/69 Pages) AD

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ADV7192

–30–

REV. 0

MODE REGISTER 0

MR0 (MR07–MR00)

(Address (SR4–SR0) = 00H)

Figure 56 shows the various operations under the control of

Mode Register 0.

MR0 BIT DESCRIPTION

Output Video Standard Selection Control (MR00–MR01)

These bits are used to set up the encoder mode. The ADV7192

can be set up to output NTSC, PAL (B, D, G, H, I), PAL M or

PAL N standard video.

Luminance Filter Select (MR02–MR04)

These bits specify which luma ﬁlter is to be selected. The ﬁlter

selection is made independent of whether PAL or NTSC is

selected.

Chrominance Filter Select (MR05–MR07)

These bits select the chrominance ﬁlter. A low-pass ﬁlter can be

selected with a choice of cutoff frequencies (0.65 MHz, 1.0 MHz,

1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF or

QCIF ﬁlters.

MODE REGISTER 1

MR1 (MR17–MR10)

(Address (SR4–SR0) = 01H)

Figure 57 shows the various operations under the control of

Mode Register 1.

MR1 BIT DESCRIPTION

DAC Control (MR10–MR15)

Bits MR15–MR10 can be used to power-down the DACs. This are

used to reduce the power consumption of the ADV7192 or if any

of the DACs are not required in the application.

Oversampling Control (MR16)

To enable 4

× Oversampling this bit has to be set to 1. When

enabled, the data is output at a frequency of 54 MHz.

Note that PLL Enable Control has to be enabled (MR61 = 0) in

× Oversampling mode. An external VREF is not recommended

in that mode.

Reserved (MR17)

A Logical 0 must be written to this bit.

MR07

MR06

MR05

MR04

MR03

MR02

MR01

MR00

CHROMA FILTER SELECT

1.3 MHz LOW-PASS FILTER

0.65 MHz LOW-PASS FILTER

1.0 MHz LOW-PASS FILTER

2.0 MHz LOW-PASS FILTER

RESERVED

CIF

QCIF

3.0 MHz LOW-PASS FILTER

MR07 MR06 MR05

MR04 MR03 MR02

LUMA FILTER SELECT

LOW-PASS FILTER (NTSC)

LOW-PASS FILTER (PAL)

NOTCH FILTER (NTSC)

NOTCH FILTER (PAL)

EXTENDED MODE

CIF

QCIF

RESERVED

MR01 MR00

NTSC

PAL (B, D, G, H, I)

PAL (M)

PAL (N)

OUTPUT VIDEO

STANDARD SELECTION

Figure 56. Mode Register 0, MR0

MR17

MR16

MR15

MR14

MR13

MR12

MR11

MR10

DAC A

DAC CONTROL

POWER-DOWN

NORMAL

MR15

DAC C

DAC CONTROL

POWER-DOWN

NORMAL

MR13

DAC E

DAC CONTROL

POWER-DOWN

NORMAL

MR11

OVERSAMPLING

CONTROL

OVERSAMPLING

MR16

DAC B

DAC CONTROL

POWER-DOWN

NORMAL

MR14

DAC D

DAC CONTROL

POWER-DOWN

NORMAL

MR12

DAC F

DAC CONTROL

POWER-DOWN

NORMAL

MR10

MR17

ZERO MUST

BE WRITTEN

TO THIS BIT

Figure 57. Mode Register 1, MR1

ADV7192 Datasheet(PDF) 30 Page - Analog Devices

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