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ADV7192 Datasheet(PDF) 8 Page - Analog Devices |
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ADV7192 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 69 page ![]() ADV7192 –8– REV. 0 t3 t2 t6 t1 t7 t5 t3 t4 t8 SDA SCL Figure 1. MPU Port Timing Diagram t9 t11 CLOCK PIXEL INPUT DATA t10 t12 HSYNC, VSYNC, BLANK Cb Y Cr Y Cb Y HSYNC, VSYNC, BLANK, CSO_HSO, VSO, CLAMP t13 t14 CONTROL I/PS CONTROL O/PS Figure 2. Pixel and Control Data Timing Diagram t16 t17 t18 TXTREQ CLOCK TXT 4 CLOCK CYCLES 4 CLOCK CYCLES 4 CLOCK CYCLES 3 CLOCK CYCLES 4 CLOCK CYCLES Figure 3. Teletext Timing Diagram t9 t10 t12 Y0 Y1 Y2 Y3 Y4 Y5 Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 t11 CLOCK Y0–Y9 INCLUDING SYNC INFORMATION Cb0–Cb9 Cr0–Cr9 PROGRESSIVE SCAN INPUT Figure 4. Progressive Scan Input Timing |
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