ADV7192 datasheet(35/69 Pages) AD

35 / 69 page

ADV7192

–35–

REV. 0

CLAMP/

VSO Select (MR77)

This bit is used to select the functionality of Pin 62. Setting this

bit to 1 selects CLAMP as the output signal. A 0 selects

VSO

as the output signal. Since this pin is also shared with the TTX

functionality, TTX Input/CLAMP–

VSO Output has to be set

accordingly (MR76).

MODE REGISTER 8

MR8 (MR87–MR80)

(Address (SR4–SR0) = 08H)

Mode Register 8 is an 8-bit-wide register. Figure 64 shows the

various operations under the control of Mode Register 8.

MR8 BIT DESCRIPTION

Progressive Scan Control (MR80)

This control enables the progressive scan inputs on pins

Y(0)/P8–Y(7)/P15, Y(8)–Y(9), Cr(0)–Cr(9), Cb(0)–Cb(9). To

enable this control MR80 has to be set to 1. It is assumed that

the incoming Y data contains all necessary sync information.

Note: Simultaneous progressive scan input and 16-bit pixel input

is not possible.

Reserved (MR81)

A 0 must be written to this bit.

Double Buffer Control (MR82)

Double Buffering can be enabled or disabled on the Contrast

Control Register, U Scale Register, V Scale Register, Hue Adjust

Control Register, Closed Captioning Register, Brightness Control

ters. Double Buffer is not available in Master Mode.

16-Bit Pixel Port (MR83)

This bit controls if the ADV7192 is operated in 8-bit or 16-bit

mode. In 8-bit mode the input data will be set up on Pins P0–P7.

Reserved (MR84)

A Logic 0 must be written to this bit.

DNR Enable Control (MR85)

To enable the DNR process this bit has to be set to 1. If this bit

is set to other DNR processing is bypassed. For further informa-

tion on DNR controls see DNR Mode Control section.

Gamma Enable Control (MR86)

To enable the programmable gamma correction this bit has

to be set to enabled (MR86 = 1). For further information on

Gamma Correction controls see Gamma Correction Registers

section.

Gamma Curve Select Control (MR87)

This bit selects which of the two programmable gamma curves is

to be used. When setting MR87 to 0, the gamma correction curve

selected is Curve A. Otherwise, Curve B is selected. Each curve

will have to be programmed by the user. For further information

on Gamma Correction controls see Gamma Correction Regis-

ters section.

MODE REGISTER 9

MR9 (MR97–MR90)

(Address (SR4–SR0) = 09H)

Mode Register 9 is an 8-bit-wide register. Figure 66 shows the

various operations under the control of Mode Register 9.

MR9 BIT DESCRIPTION

Undershoot Limiter (MR90–MR91)

This control ensures that no luma video data will go below a

programmable level. This prevents any synchronization problems

due to luma signals going below the blanking level. Available

limit levels are –1.5 IRE, –6 IRE, –11 IRE. Note that this facility is

only available in 4

× Oversampling mode (MR16 = 1). When the

device is operated in 2

× Oversampling mode (MR16 = 0) or RGB

output without RGB sync are selected, the minimum luma level is

set in Timing Register 0, TR06 (Min Luma Control).

Black Burst Y DAC (MR92)

It is possible to output a Black Burst signal from the DAC

which is selected to be the Luma DAC (MR22, MR21, MR20).

This signal can be useful for locking two video sources together

using professional video equipment. See also Black Burst Out-

put section.

Black Burst Luma (MR93)

It is possible to output a Black Burst signal from the DAC which

is selected to be the Y-DAC (MR22, MR21, MR20). This signal

can be useful for locking two video sources together using pro-

fessional video equipment. See also Black Burst Output section.

20 IRE

0 IRE

–20 IRE

–40 IRE

21.5 IRE

0 IRE

–21.5 IRE

–43 IRE

3.58MHz

COLOR BURST

(9 CYCLES)

4.43MHz

COLOR BURST

(10 CYCLES)

NTSC BLACK BURST SIGNAL

PAL BLACK BURST SIGNAL

Figure 65. Black Burst Signals for PAL and NTSC Standards

ZERO SHOULD

BE WRITTEN

TO THIS BIT

MR84

MR87

MR86

MR85

MR84

MR83

MR82

MR81

MR80

MR83

16-PIXEL

PORT CONTROL

DISABLE

ENABLE

DNR ENABLE

CONTROL

MR85

DISABLE

ENABLE

DISABLE

ENABLE

MR82

DOUBLE BUFFER

CONTROL

DISABLE

ENABLE

MR86

GAMMA ENABLE

CONTROL

CURVE A

CURVE B

MR87

GAMMA CURVE

SELECT CONTROL

ZERO SHOULD

BE WRITTEN

TO THIS BIT

MR81

DISABLE

ENABLE

MR80

PROGRESSIVE

SCAN CONTROL

Figure 64. Mode Register 8, MR8

ADV7192 Datasheet(PDF) 35 Page - Analog Devices

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