ADV7192 datasheet(12/69 Pages) AD

12 / 69 page

ADV7192

–12–

REV. 0

Digital Noise Reduction allows improved picture quality in remov-

ing low amplitude, high frequency noise. Figure 6 shows the DNR

functionality in the two modes available.

Programmable gamma correction is also available. The figure below

shows the response of different gamma values to a ramp signal.

250

200

150

100

300

SIGNAL OUTPUTS

SIGNAL

INPUT

0.5

GAMMA CORRECTION BLOCK OUTPUT

TO A RAMP INPUT FOR VARIOUS GAMMA VALUES

100

150

200

250

LOCATION

0.3

1.5

1.8

Figure 7. Signal Input (Ramp) and Selectable Gamma

Output Curves

The device is driven by a 27 MHz clock. Data can be output at

27 MHz or 54 MHz (on-board PLL) when 4

oversampling is

enabled. Also, the output filter requirements in 4

oversampling

and 2

oversampling differ, as can be seen in Figure 8.

–30dB

0dB

6.75MHz

13.5MHz

27.0MHz

40.5MHz

54.0MHz

FILTER

REQUIREMENTS

FILTER

REQUIREMENTS

Figure 8. Output Filter Requirements in 4

× Oversampling

Mode

ENCODER

CORE

54MHz

OUTPUT

RATE

ADV7192

PLL

54MHz

MPEG2

PIXEL BUS

27MHz

Figure 9. PLL and 4

× Oversampling Block Diagram

The ADV7192 also supports both PAL and NTSC square pixel

operation. In this case the encoder requires a 24.5454 MHz Clock

for NTSC or 29.5 MHz Clock for PAL square pixel mode opera-

tion. All internal timing is generated on-chip.

An advanced power management circuit enables optimal control

of power consumption in normal operating modes or sleep modes.

The Output Video Frames are synchronized with the incoming

data Timing Reference Codes. Optionally, the Encoder accepts

(and can generate) HSYNC, VSYNC, and FIELD timing signals.

These timing signals can be adjusted to change pulsewidth and

position while the part is in master mode.

HSO/CSO and VSO TTL outputs are also available and are timed

to the analog output video.

A separate teletext port enables the user to directly input teletext

data during the vertical blanking interval.

The ADV7192 also incorporates WSS and CGMS-A data control

generation.

The ADV7192 modes are set up over a 2-wire serial bidirectional

port (I

2C-compatible) with two slave addresses, and the device

is register-compatible with the ADV7172.

The ADV7192 is packaged in an 80-lead LQFP package.

DATA PATH DESCRIPTION

For PAL B, D, G, H, I, M, N, and NTSCM, N modes, YCrCb

4:2:2 data is input via the CCIR-656/601-compatible Pixel Port

at a 27 MHz Data Rate. The Pixel Data is demultiplexed to form

three data paths. Y typically has a range of 16 to 235, Cr and Cb

typically have a range of 128 112; however, it is possible to

input data from 1 to 254 on both Y, Cb, and Cr. The ADV7192

supports PAL (B, D, G, H, I, N, M) and NTSCM, N (with

and without Pedestal) and PAL60 standards.

Digital noise reduction can be applied to the Y signal. Pro-

grammable gamma correction can also be applied to the Y

signal if required.

The Y data can be manipulated for contrast control and a setup

level can be added for brightness control. The Cr, Cb data can

be scaled to achieve color saturation control. All settings become

effective at the start of the next ﬁeld when double buffering is

enabled.

The appropriate sync, blank, and burst levels are added to the

YCrCb data. Macrovision antitaping, closed-captioning and

teletext levels are also added to Y and the resultant data is inter-

polated to 54 MHz (4

Oversampling Mode). The interpolated

data is ﬁltered and scaled by three digital FIR ﬁlters.

The U and V signals are modulated by the appropriate Subcarrier

Sine/Cosine waveforms and a phase offset may be added onto

the color subcarrier during active video to allow hue adjustment.

The resulting U and V signals are added together to make up

the Chrominance signal. The Luma (Y) signal can be delayed

by up to six clock cycles (at 27 MHz) and the Chroma signal

can be delayed by up to eight clock cycles (at 27 MHz).

The Luma and Chroma signals are added together to make up

the Composite Video Signal. All timing signals are controlled.

The YCrCb data is also used to generate RGB data with appropri-

ate sync and blank levels. The YUV levels are scaled to output

the suitable SMPTE/EBU N10, MII, or Betacam levels.

Each DAC can be individually powered off if not required. A

complete description of DAC output conﬁgurations is given in

the Mode Register 2 section.

Video output levels are illustrated in Appendix 9.

ADV7192 Datasheet(PDF) 12 Page - Analog Devices

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