ADV7192 datasheet(9/69 Pages) AD

9 / 69 page

ADV7192

–9–

REV. 0

ABSOLUTE MAXIMUM RATINGS

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on any Digital Input Pin . . GND – 0.5 V to VAA + 0.5 V

Storage Temperature (TS) . . . . . . . . . . . . . . –65

°C to +150°C

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150

°C

Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 220

°C

Analog Outputs to GND

. . . . . . . . . . . . GND – 0.5 V to VAA

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections

of this speciﬁcation is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

2Analog Output Short Circuit to any Power Supply or Common can be of an

indeﬁnite duration.

PACKAGE THERMAL PERFORMANCE

The 80-lead package is used for this device. The junction-to-

ambient (

JA) thermal resistance in still air on a four-layer PCB

is 24.7

°C.

To reduce power consumption when using this part the user

can run the part on a 3.3 V supply, turn off any unused DACs.

The user must at all times stay below the maximum junction

temperature of 110

°C. The following equation shows how to

calculate this junction temperature:

Junction Temperature = (VAA

× (IDAC + ICCT)) × θJA + 70°C TAMB

IDAC = 10 mA + (sum of the average currents consumed by

each powered-on DAC)

Average current consumed by each powered-on DAC =

(VREF

× K )/R

SET

VREF = 1.235 V

K = 4.2146

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADV7192KST

°C to 70°C

80-Lead Quad Flatpack

ST-80

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADV7192 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN CONFIGURATION

NC = NO CONNECT

Y[0]/P8

Y[1]/P9

Y[2]/P10

Y[3]/P11

Y[4]/P12

Y[5]/P13

Y[6]/P14

Y[7]/P15

Y[8]

Y[9]

VREF

COMP 1

DAC A

DAC B

VAA

AGND

DAC C

DAC D

AGND

VAA

DAC E

DAC F

COMP 2

RSET2

DGND

RESET

PAL_NTSC

RSET1

ALSB

SCRESET/RTC/TR

80 79 78 77 76

71 70 69 68 67 66 65

75 74 73 72

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

ADV7192

LQFP

ADV7192 Datasheet(PDF) 9 Page - Analog Devices

ADV7192 Datasheet(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Datasheet Download

Link URL