ADV7192 datasheet(18/69 Pages) AD

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ADV7192

–18–

REV. 0

UNDERSHOOT LIMITER

A limiter is placed after the digital ﬁlters. This prevents any

synchronization problems for TVs. The level of undershoot is

programmable between –1.5 IRE, –6 IRE, –11 IRE when oper-

ating in 4

× Oversampling Mode. In 2× Oversampling Mode the

limits are –7.5 IRE and 0 IRE. (Mode Register 9 and Timing

DIGITAL NOISE REDUCTION

DNR is applied to the Y data only. A ﬁlter block selects the

high frequency, low amplitude components of the incoming

signal (DNR Input Select). The absolute value of the ﬁlter output

is compared to a programmable threshold value (DNR Thresh-

old Control). There are two DNR modes available: DNR Mode

and DNR Sharpness Mode.

In DNR Mode, if the absolute value of the ﬁlter output is smaller

than the threshold, it is assumed to be noise. A programmable

amount (Coring Gain Control) of this noise signal will be sub-

tracted from the original signal.

In DNR Sharpness Mode, if the absolute value of the ﬁlter output

is less than the programmed threshold, it is assumed to be noise,

as before. Otherwise, if the level exceeds the threshold, now

being identiﬁed as a valid signal, a fraction of the signal (Coring

Gain Control) will be added to the original signal in order to boost

high frequency components and to sharpen the video image.

In MPEG systems it is common to process the video information

in blocks of 8

× 8 pixels for MPEG2 systems, or 16 × 16 pixels

for MPEG1 systems ('Block Size Control'). DNR can be applied

to the resulting block transition areas that are known to contain

noise. Generally the block transition area contains two pixels. It

is possible to deﬁne this area to contain four pixels (Border Area

Control).

It is also possible to compensate for variable block positioning or

differences in YCrCb pixel timing with the use of the Block Offset

Control. (Mode Register 8, DNR Registers 0–2.)

DOUBLE BUFFERING

Double buffering can be enabled or disabled on the following

registers: Closed Captioning Registers, Brightness Control Reg-

ister, V-Scale, U-Scale Contrast Control Register, Hue Adjust

bit. These registers are updated once per ﬁeld on the falling

edge of the VSYNC signal. Double Buffering improves the overall

performance of the ADV7192, since modiﬁcations to register

settings will not be made during active video, but take effect on

the start of the active video. (Mode Register 8.)

GAMMA CORRECTION CONTROL

Gamma correction may be performed on the luma data. The

user has the choice to use either of two different gamma curves,

A or B. At any one time one of these curves is operational if

gamma correction is enabled. Gamma correction allows the

mapping of the luma data to a user-deﬁned function. (Mode

NTSC PEDESTAL CONTROL

In NTSC mode it is possible to have the pedestal signal gener-

ated on the output video signal. (Mode Register 2.)

POWER-ON RESET

After power-up, it is necessary to execute a RESET operation. A

reset occurs on the falling edge of a high-to-low transition on the

RESET pin. This initializes the pixel port such that the data on

the pixel inputs pins is ignored. See Appendix 8 for the register

settings after RESET is applied.

PROGRESSIVE SCAN INPUT

It is possible to input data to the ADV7192 in progressive scan

format. For this purpose the input pins Y0/P8–Y7/P15, Y8–Y9,

Cr0–Cr9 and Cb0–Cb9 accept 10-bit Y data, 10-bit Cb data

and 10-bit Cr data. The data is clocked into the part at 27 MHz.

The data is then ﬁltered and sinc corrected in an 2

Interpo-

lation ﬁlter and then output to three video DACs at 54 MHz

(to interface to a progressive scan monitor).

FREQUENCY – MHz

030

–10

–20

–30

–50

–60

–40

–70

Figure 32. Plot of the Interpolation Filter for the Y Data

FREQUENCY – MHz

030

–10

–20

–30

–50

–60

–40

–70

Figure 33. Plot of the Interpolation Filter for the CrCb Data

It is assumed that there is no color space conversion or any other

such operation to be performed on the incoming data. Thus if

these DAC outputs are to drive a TV, all relevant timing and

synchronization data should be contained in the incoming digital

Y data.

The block diagram below shows a possible conﬁguration for

progressive scan mode using the ADV7192.

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