WM8903 datasheet(118/178 Pages) WOLFSON

118 / 178 page

WM8903

Production Data

PD, Rev 4.5, June 2012

118

CONTROL WRITE SEQUENCER

The Control Write Sequencer is a programmable unit that forms part of the WM8903 control interface

logic. It provides the ability to perform a sequence of register write operations with the minimum of

demands on the host processor - the sequence may be initiated by a single operation from the host

processor and then left to execute independently.

Default sequences for Start-Up and Shut-Down are provided (see “Default Sequences” section). It is

recommended that these default sequences are used unless changes become necessary.

When a sequence is initiated, the sequencer performs a series of pre-defined register writes. The

host processor informs the sequencer of the start index of the required sequence within the

sequencer’s memory. At each step of the sequence, the contents of the selected register fields are

read from the sequencer’s memory and copied into the WM8903 control registers. This continues

sequentially through the sequencer’s memory until an “End of Sequence” bit is encountered; at this

point, the sequencer stops and an Interrupt status flag is asserted. For cases where the timing of the

write sequence is important, a programmable delay can be set for specific steps within the sequence.

Note that the Control Write Sequencer’s internal clock is derived from the internal clock CLK_SYS. An

external MCLK signal must be present when using the Control Write Sequencer, and CLK_SYS must

be enabled by setting CLK_SYS_ENA (see “Clocking and Sample Rates”). The clock division from

MCLK is handled transparently by the WM8903 without user intervention, as long as MCLK and

sample rates are set correctly.

INITIATING A SEQUENCE

The Register fields associated with running the Control Write Sequencer are described in Table 76.

The Write Sequencer Clock is enabled by setting the WSMD_CLK_ENA bit. Note that the operation of

the Control Write Sequencer also requires the internal clock CLK_SYS to be enabled via the

CLK_SYS_ENA (see “Clocking and Sample Rates”).

The start index of the required sequence must be written to the WSEQ_START_INDEX field. Setting

the WSEQ_START bit initiates the sequencer at the given start index.

The Write Sequencer can be interrupted by writing a logic 1 to the WSEQ_ABORT bit.

The current status of the Write Sequencer can be read using two further register fields - when the

WSEQ_BUSY bit is asserted, this indicates that the Write Sequencer is busy. Note that, whilst the

Control Write Sequencer is running a sequence (indicated by the WSEQ_BUSY bit), normal

read/write operations to the Control Registers cannot be supported. (The Write Sequencer registers

and the Software Reset register can still be accessed when the Sequencer is busy.) The index of the

current step in the Write Sequencer can be read from the WSEQ_CURRENT_INDEX field; this is an

indicator of the sequencer’s progress. On completion of a sequence, this field holds the index of the

last step within the last commanded sequence.

When the Write Sequencer reaches the end of a sequence, it asserts the WSEQ_BUSY_EINT flag in

Interrupt Event on completion of the sequence. Note that the WSEQ_BUSY_EINT flag is asserted to

indicate that the WSEQ is NOT Busy.

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