WM8903 datasheet(122/178 Pages) WOLFSON

122 / 178 page

WM8903

Production Data

PD, Rev 4.5, June 2012

122

DEFAULT SEQUENCES

When the WM8903 is powered up, two Control Write Sequences are available through default

settings in both RAM and ROM memory locations. The purpose of these sequences, and the register

write required to initiate them, is summarised in Table 78. In both cases, a single register write will

initiate the sequence.

WSEQ START

INDEX

WSEQ FINISH

INDEX

PURPOSE

TO INITIATE

0 (00h)

29 (1Dh)

Start-Up sequence

Write 0100h to

32 (20h)

48 (30h)

Shutdown sequence

Write 0120h to

Table 78 Write Sequencer Default Sequences

Note on Shut-Down sequence: The instruction at Index Address 32 (20h) shorts the outputs

LINEOUTL and LINEOUTR. If the Line outputs are not in use at the time the sequence is run, then

the sequence could, instead, be started at Index Address 33.

Index addresses 0 to 31 may be programmed to users’ own settings at any time, as described in

“Programming a Sequence” Users’ own settings remain in memory and are not affected by software

resets (i.e. writing to Register R0). However, any non-default sequences are lost when the device is

powered down.

START-UP SEQUENCE

The Start-up sequence is initiated by writing 0100h to Register R111 (6Fh). This single operation

starts the Control Write Sequencer at Index Address 0 (00h) and executes the sequence defined in

Table 79.

For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately 425ms

to run.

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

0 (00h)

R4 (04h)

5 bits

Bit 0

1Ah

POBCTRL = 1

ISEL [1:0] = 10b

STARTUP_BIAS_ENA = 1

BIAS_ENA = 0

(delay = 0.5625ms)

1 (01h)

R65 (41h)

1 bit

Bit 1

01h

SPK_DISCHARGE = 1

(delay = 32.5ms)

2 (02h)

R17 (11h)

2 bits

Bit 0

03h

SPKL_ENA = 1

SPKR_ENA = 1

(delay = 0.5625ms)

3 (03h)

R65 (41h)

1 bit

Bit 1

00h

SPK_DISCHARGE = 0

(delay = 0.5625ms)

4 (04h)

R5 (5h)

8 bits

Bit 0

F7h

VMID_TIE_ENA = 1

BUFIO_ENA = 1

VMID_IO_ENA = 1

VMID_SOFT = 10

VMID_RES = 11

VMID_BUF_ENA = 1

(delay = 128.5ms)

5 (05h)

R17 (11h)

2 bits

Bit 0

00h

SPKL_ENA = 0

SPKR_ENA = 0

(delay = 0.5625ms)

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