WM8903 datasheet(123/178 Pages) WOLFSON

123 / 178 page

Production Data

WM8903

PD, Rev 4.5, June 2012

123

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

6 (06h)

R5 (5h)

2 bits

Bit 3

00h

VMID_SOFT = 00

(delay = 0.5625ms)

7 (07h)

R5 (05h)

2 bits

Bit 1

01h

VMID_RES [1:0] = 01b

(delay = 0.5625ms)

8 (08h)

R4 (04h)

1 bit

Bit 0

01h

BIAS_ENA = 1

(delay = 0.5625ms)

9 (09h)

R14 (0Eh)

2 bits

Bit 0

03h

HPL_PGA_ENA = 1

HPR_PGA_ENA = 1

(delay = 0.5625ms)

10 (0Ah)

R13 (Dh)

2 bits

Bit 0

03h

MIXOUTL = 1

MIXOUTR = 1

(delay = 0.5625ms)

11 (0Bh)

R15 (0Fh)

2 bits

Bit 0

03h

LINEOUTL_PGA_ENA = 1

LINEOUTR_PGA_ENA = 1

(delay = 0.5625ms)

12 (0Ch)

R22 (16h)

1 bit

Bit 1

01h

CLK_DSP_ENA = 1

(delay = 0.5625ms)

13 (0Dh)

R18 (12h)

2 bits

Bit 2

03h

DACL_ENA = 1

DACR_ENA = 1

(delay = 2.5ms)

14 (0Eh)

R255 (FFh)

1 bit

Bit 0

00h

Dummy Write for expansion

(delay = 0.5625ms)

15 (0Fh)

R4 (04h)

1 bit

Bit 4

00h

POBCTRL = 0

(delay = 0.5625ms)

16 (10h)

R98 (62h)

1 bit

Bit 0

01h

CP_ENA = 1

(delay = 4.5ms)

17 (11h)

R255 (FFh)

1 bit

Bit 0

00h

Dummy Write for expansion

(delay = 0.5625ms)

18 (12h)

R90 (5Ah)

8 bits

Bit 0

11h

HPL_ENA = 1

HPR_ENA = 1

(delay = 0.5625ms)

19 (13h)

R94 (5Eh)

8 bits

Bit 0

11h

LINEOUTL_ENA = 1

LINEOUTR_ENA = 1

(delay = 0.5625ms)

20 (14h)

R90 (5Ah)

8 bits

Bit 0

33h

HPL_ENA_DLY = 1

HPR_ENA_DLY = 1

(delay = 0.5625ms)

21 (15h)

R94 (5Eh)

8 bits

Bit 0

33h

LINEOUTL_ENA_DLY = 1

LINEOUTR_ENA_DLY = 1

(delay = 0.5625ms)

22 (16h)

R69 (45h)

2 bits

Bit 0

02h

DCS_MODE = 10

(delay = 0.5625ms)

23 (17h)

R67 (43h)

4 bits

Bit 0

0Fh

DCS_ENA = 1111

(delay = 256.5ms)

24 (18h)

R67 (43h)

4 bits

Bit 0

0Fh

DCS_ENA = 1111

(delay = 8.5ms)

25 (19h)

R255 (FFh)

1 bit

Bit 0

00h

Dummy Write for expansion

(delay = 0.5625ms)

26 (1Ah)

R90 (5Ah)

8 bits

Bit 0

77h

HPL_ENA_OUTP = 1

HPR_ENA_OUTP = 1

(delay = 0.5625ms)

WM8903 Datasheet(PDF) 123 Page - Wolfson Microelectronics plc

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