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WM8903 Datasheet(PDF) 125 Page - Wolfson Microelectronics plc |
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WM8903 Datasheet(HTML) 125 Page - Wolfson Microelectronics plc |
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125 / 178 page ![]() Production Data WM8903 w PD, Rev 4.5, June 2012 125 SHUTDOWN SEQUENCE The Shutdown sequence is initiated by writing 0120h to Register R111 (6Fh). This single operation starts the Control Write Sequencer at Index Address 32 (20h) and executes the sequence defined in Table 80. For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately 325ms to run. WSEQ INDEX REGISTER ADDRESS WIDTH START DATA DELAY EOS DESCRIPTION 32 (20h) R94 (5Eh) 8 bits Bit 0 77h 0h 0b LINEOUTL_RMV_SHORT = 0 LINEOUTR_RMV_SHORT = 0 (delay = 0.5625ms) 33 (21h) R90 (5Ah) 8 bits Bit 0 77h 0h 0b HPL_RMV_SHORT = 0 HPR_RMV_SHORT = 0 (delay = 0.5625ms) 34 (22h) R90 (5Ah) 8 bits Bit 0 00h 0h 0b HPL_ENA_OUTP = 0 HPL_ENA_DLY = 0 HPL_ENA = 0 HPR_ENA_OUTP = 0 HPR_ENA_DLY = 0 HPR_ENA = 0 (delay = 0.5625ms) 35 (23h) R94 (5Eh) 8 bits Bit 0 00h 0h 0b LINEOUTL_ENA_OUTP = 0 LINEOUTL_ENA_DLY = 0 LINEOUTL_ENA = 0 LINEOUTR_ENA_OUTP = 0 LINEOUTR_ENA_DLY = 0 LINEOUTR_ENA = 0 (delay = 0.5625ms) 36 (24h) R67 (43h) 4 bits Bit 0 00h 0h 0b DCS_ENA = 0000 (delay = 0.5625ms) 37 (25h) R98 (62h) 1 bit Bit 0 00h 0h 0b CP_ENA = 0 (delay = 0.5625ms) 38 (26h) R18 (12h) 2 bits Bit 2 00h 0h 0b DACL_ENA = 0 DACR_ENA = 0 (delay = 0.5625ms) 39 (27h) R22 (16h) 1 bit Bit 1 00h 0h 0b CLK_DSP_ENA = 0 (delay = 0.5625ms) 40 (28h) R14 (0Eh) 2 bits Bit 0 00h 0h 0b HPL_PGA_ENA = 0 HPR_PGA_ENA = 0 (delay = 0.5625ms) 41 (29h) R15 (0Fh) 2 bits Bit 0 00h 0h 0b LINEOUTL_PGA_ENA = 0 LINEOUTR_PGA_ENA = 0 (delay = 0.5625ms) 42 (2Ah) R13 (0Dh) 2 bits Bit 0 00h 0h 0b MIXOUTL_ENA = 0 MIXOUTR_ENA = 0 (delay = 0.5625ms) 43 (2Bh) R4 (04h) 1 bit Bit 0 00h 0h 0b BIAS_ENA = 0 (delay = 0.5625ms) 44 (2Ch) R5 (05h) 2 bits Bit 3 02h 0h 0b VMID_SOFT = 10 (delay = 0.5625ms) 45 (2Dh) R5 (05h) 1 bit Bit 0 00h Ch 0b VMID_BUF_ENA = 0 (delay = 256.5ms) 46 (2Eh) R5 (05h) 1 bit Bit 0 00h 9h 0b VMID_BUF_ENA = 0 |
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