WM8903 datasheet(129/178 Pages) WOLFSON

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Production Data

WM8903

PD, Rev 4.5, June 2012

129

QUICK START-UP AND SHUTDOWN

The WM8903 has the capability to perform a quick start-up and shut-down with a minimum number of

default start-up settings that set up the device for DAC playback via Headphone and Line Output.

Assuming a 12.288MHz external clock, the start-up sequence configures the device for 48kHz

playback mode.

The default start-up sequence requires three register write operations. The default shutdown

sequence requires just a single register write. The minimum procedure for executing the quick start-

up and shutdown sequences is described below. See “Control Write Sequencer” for more details.

QUICK START-UP (DEFAULT SEQUENCE)

An external clock must be applied to MCLK. Assuming 12.288MHz input clock, the start-up sequence

will take approximately 425ms to complete.

The following register operations will initiate the quick start-up sequence.

ADDRESS

VALUE

DESCRIPTION

R108 (6Ch)

Write Sequencer 0

0100h

WSMD_CLK_ENA = 1

This enables the Write Sequencer Clock

R22 (16h)

Clock Rates 2

0004h

CLK_SYS_ENA = 1

This enables the System Clock

R111 (6Fh)

Write Sequencer 3

0100h

WSEQ_START_INDEX = 00h

WSEQ_START = 1

WSEQ_ABORT = 0

This starts the Write Sequencer at Index address 0 (00h)

Table 82 Quick Start-Up Control

The WSEQ_BUSY bit (in Register R112, see Table 76) will be set to 1 while the sequence runs.

When this bit returns to 0, the device has been set up and is ready for DAC playback operation.

QUICK SHUTDOWN (DEFAULT SEQUENCE)

The default shutdown sequence assumes the initial device conditions are as configured by the default

start-up sequence. Assuming 12.288MHz input clock, the shutdown sequence will take approximately

325ms to complete.

The following register operation will initiate the default shut-down sequence.

ADDRESS

VALUE

DESCRIPTION

R111 (6Fh)

Write Sequencer 3

0120h

WSEQ_START_INDEX = 20h

WSEQ_START = 1

WSEQ_ABORT = 0

This starts the Write Sequencer at Index address 32 (20h)

Table 83 Quick Shutdown Control

The WSEQ_BUSY bit (in Register R112, see Table 76) will be set to 1 while the sequence runs.

When this bit returns to 0, the system clock can be disabled (CLK_SYS_ENA=0) and MCLK can be

stopped.

WM8903 Datasheet(PDF) 129 Page - Wolfson Microelectronics plc

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