ACE25C200

2MB Serial Flash Memory

VER 1.2

20

Chip Erase (CE) (C7h / 60h)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A

Write Enable instruction must be executed before the device will accept the Chip Erase Instruction

(Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and

shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure

17.

The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip

Erase instruction will not be executed. After CS# is driven high, the self -timed Chip Erase instruction

Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the

status of the WIP bit. The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished

and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the

Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase in struction will not

be executed if any page is protected by the Block Protect (BP2, BP1, and BP0) bits.

Figure 17 Chip erase instruction

Power-down (B9h)

Although the standby current during normal operation is relatively low, standby current ca n be further

reduced with the Power-down instruction. The lower power consumption makes the Power-down

Characteristics”). The instruction is initiated by driving the CS# pin low and shifting the instruction

code “B9h” as shown in Figure 18.

The CS# pin must be driven high after the eighth bit has been latched. If this is not done the

Power-down instruction will not be executed. After CS# is driven high, the power-down state will enter

state only the Release from Power- down / Device ID instruction, which restores the device to normal

operation, will be recognized. All other instructions are ignored. This includes the Read Status

Register instruction, which is always available during normal operation. Ignoring all but one

instruction makes the Power Down state a useful condition for securing maximum write p rotection.