ACE25C200

2MB Serial Flash Memory

VER 1.2

5

Block (64KB)

Sector (4KB)

Address Range

3

63

03F000h

03FFFFh

…

…

…

48

030000h

030FFFh

2

47

02F000h

02FFFFh

…

…

…

32

020000h

020FFFh

1

31

01F000h

01FFFFh

…

…

…

16

010000h

010FFFh

0

15

00F000h

00FFFFh

…

…

…

2

002000h

002FFFh

1

001000h

001FFFh

0

000000h

000FFFh

Device Operations

Standard SPI

The ACE25C200 is accessed through an SPI compatible bus consisting of four signals: Serial Clock

(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI

instructions use the DI input pin to serially write instructions, addresses or data to the device on the

rising edge of CLK. The DO output pin is used to read data or status from the device on the falling

edge of CLK.

SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0

and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and

data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the

falling and rising edges of CS#. For Mode 3, the CLK signal is normally high on the falling and rising

edges of CS#.

Figure 2 The difference between Mode 0 and Mode 3