ACE25C200

2MB Serial Flash Memory

VER 1.2

11

Dual SPI instructions Set

Instruction Name

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Clock number

(0-7)

(8-15)

(16-23)

(24-31)

(32-39)

(40-47)

Fast read dual output

3Bh

A23-A16

A15-A8

A7-A0

dummy

(D7-

Fast read dual I/O

BBh

A23-A8

(5)

A7-A0, M7-M0

(5)

(D7-

Notes:

1.

Data bytes are shifted with Most Significant Bit first. Byte fields with data in

parenthesis “( )” indicate data output from the

device on 1 or 2 DQ pins.

2.

The Status Register contents and Device ID will repeat continuously until CS# terminates the instruction.

3.

At least one byte of data input is required for Page Program and Program Security Sectors, up to 256 bytes of data input. If

more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite

previously sent data.

4.

See Table 3 Manufacturer and Device Identification table for device ID information.

5.

Dual SPI address input format:

6.

Write Enable (WREN) (06h)

The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status

Register to a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase,

Chip Erase, Write Status Register instruction. The Write Enable (WREN) instruction is entered by

driving CS# low, shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of

CLK, and then driving CS# high.

Figure 5 Write enable instruction

Write disable (WRDI) (04h)

The Write Disable (WRDI) instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status

Register to a 0. The Write Disable (WRDI) instruction is entered by driving CS# low, shifting th e

instruction code “04h” into the DI pin and then driving CS# high. Note that the WEL bit is automatically

reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,

Block Erase, Chip Erase instructions.