ACE25C200

2MB Serial Flash Memory

VER 1.2

16

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after

CS# is raised and then lowered) does not require the BBh instruction code, as shown in Figure 13.

This reduces the instruction sequence by eight clocks and allows the Read address to be immediately

entered after CS# is asserted low. If the “

Continuous Read Mode” bits M5-4 do not equal to (1,0),

the next instruction (after CS# is raised and then lowered) requires the first byte instruction code, thus

Figure 12 Fast read dual I/O instruction (initial instruction or previous M5-4≠10)