ACE25C200

2MB Serial Flash Memory

VER 1.2

13

To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously

have been executed for the device to accept the Write Status Register (WRSR)

instruction (Status

Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving CS# low,

sending the instruction code “01h”, and then writing the status register data byte as illustrated in

Figure 8.

To complete the Write Status Register (WRSR) instruction, the CS# pin must be driven high after the

eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register (WRSR)

instruction will not be executed.

During non-volatile Status Register write operation (06h combined with 01h), after CS# is driven high,

Electrical Characteristics”). While the Write Status Register cycle is in progress, the Read Status

Register instruction may still be accessed to check the status of the WIP bit. The WIP bit is a 1 during

the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other

instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit

in the Status Register will be cleared to 0.

Figure 8 Writes status register instruction

Read Data (03h)

The Read Data instruction allows one or more data bytes to be sequentially read from the memory.

The instruction is initiated by driving the CS# pin low and then shifting the instruction code “03h”

followed by a 24-bit address A23-A0 into the DI pin. The code and address bits are latched on the

rising edge of the CLK pin. After the address is received, the data byte of the addressed memory

location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first.

The address is automatically incremented to the next higher address after each byte o f data is shifted

out allowing for a continuous stream of data. This means that the entire memory can be accessed with

a single instruction as long as the clock continues. The instruction is completed by driving CS# high.

The Read Data instruction sequence is shown in Figure 9. If a Read Data instruction is issued while

an Erase, Program or Write cycle is in process (WIP =1) the instruction is ignored and will not have

any effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a

The Read Data (03h) instruction is only supported in Standard SPI mode.