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ADS42LB49 Datasheet(PDF) 1 Page - Texas Instruments |
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ADS42LB49 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 70 page  CLKINP, M CLKIN INAP, M INA Device Configuration Common Mode VCM DA1P, M DA1 DB1P, DB1M DA0P, M DA0 DB0P, DB0M 14-, 16-Bit ADC JESD204B Digital INBP, M INB Digital Block Gain Test Modes JESD204B Digital Digital Block Gain Test Modes Device SYSREFP, M SYSREF PLL x10, x20 SYNCP, M SYNC Divide by 1, 2, 4 OVRA OVRB Delay 14-, 16-Bit ADC -120 -100 -80 -60 -40 -20 0 0 25 50 75 100 125 Frequency (MHz) FFT for 170MHz Input Signal Fs = 250Msps Fin = 170MHz Ain = -1dBFS HD2 = 90dBc HD3 = 89dBc Non HD2,3 = 100dBc ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters Check for Samples: ADS42JB49, ADS42JB69 1 FEATURES APPLICATIONS 2 • Dual-Channel ADCs • Communication and Cable Infrastructure • 14- and 16-Bit Resolution • Multi-Carrier, Multimode Cellular Receivers • Maximum Clock Rate: 250 MSPS • Radar and Smart Antenna Arrays • JESD204B Serial Interface • Broadband Wireless – Subclass 0, 1, 2 Compliant • Test and Measurement Systems – Up to 3.125 Gbps • Software-Defined and Diversity Radios – Two and Four Lanes Support • Microwave and Dual-Channel I/Q Receivers • Analog Input Buffer with High-Impedance Input • Repeaters • Flexible Input Clock Buffer: • Power Amplifier Linearization Divide-by-1, -2, and -4 DESCRIPTION • Differential Full-Scale Input: 2 VPP and 2.5 VPP The ADS42JB69 and ADS42JB49 are high-linearity, (Register Programmable) dual-channel, 16- and 14-bit, 250-MSPS, analog-to- • Package: 9-mm × 9-mm QFN-64 digital converters (ADCs). These devices support the • Power Dissipation: 850 mW/Ch JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides • Aperture Jitter: 85 fS rms uniform input impedance across a wide frequency • Internal Dither range while minimizing sample-and-hold glitch energy • Channel Isolation: 100 dB making it easy to drive analog inputs up to very high • Performance: input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. – fIN = 170 MHz at 2 VPP, –1 dBFS The devices employ internal dither algorithms to – SNR: 73.3 dBFS provide excellent spurious-free dynamic range – SFDR: 93 dBc for HD2, HD3 (SFDR) over a large input frequency range. – SFDR: 100 dBc for Non HD2, HD3 RELATED PRODUCTS – fIN = 170 MHz at 2.5 VPP, –1 dBFS INTERFACE 14-BIT, 14-BIT, 16-BIT, – SNR: 74.7 dBFS OPTION 160 MSPS 250 MSPS 250 MSPS – SFDR: 89 dBc for HD2, HD3 and DDR, — ADS42LB49 ADS42LB69 QDR LVDS 95 dBc for Non HD2, HD3 JESD204B ADS42JB46 ADS42JB49 ADS42JB69 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains Copyright © 2012–2013, Texas Instruments Incorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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