| Electronic Components Datasheet Search |
|
10XSC425 Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
10XSC425 Datasheet(HTML) 33 Page - Freescale Semiconductor, Inc |
|
33 / 56 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 33 10XSC425 6.2.2 Normal Mode The 10XSC425 is in Normal mode when: •VPWR and VDD are within the normal voltage range, • wake-up = 1, • fail = 0, •fault = 0. In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:3] are under control, as defined by hson signal: hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en ) or (On bit [x] and Duty_cycle[x] and PWM_en). In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined by the following: fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en ) or (On bit [x]). 6.2.2.1 Programmable PWM Module The outputs HS[0:3] are controlled by the programmable PWM module if PWM_en and the On bits are set to logic [1]. The clock frequency from IN0 input pin or from internal clock is the factor 27 (128) of the output PWM frequency (CLOCK_sel bit). The outputs HS[0:3] can be controlled in the range of 5.0 to 98% with a resolution of seven bits of duty cycle (Table 7). The state of other IN pin is ignored. The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC behavior of the light module (Table 8). The clock frequency from IN0 is permanently monitored in order to report a clock failure in case the frequency is out of the specified frequency range (from fIN0(LOW) to fIN0(HIGH)). In case of a clock failure, no PWM feature is provided, the On bit defines the outputs state and the CLOCK_fail bit reports [1]. Table 7. Output PWM Resolution On bit Duty cycle Output state 0 X OFF 1 0000000 PWM (1/128 duty cycle) 1 0000001 PWM (2/128 duty cycle) 1 0000010 PWM (3/128 duty cycle) 1 n PWM ((n+1)/128 duty cycle) 1 1111111 fully ON Table 8. Output PWM Switching Delay Delay bits Output delay 000 no delay 001 16 PWM clock periods 010 32 PWM clock periods 011 48 PWM clock periods 100 64 PWM clock periods 101 80 PWM clock periods 110 96 PWM clock periods 111 112 PWM clock periods |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |