10XSC425 datasheet(40/56 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

10XSC425

6.3.7

Ground Disconnect Protection

In the event the 10XSC425 ground is disconnected from load ground, the device protects itself and safely turns OFF the output,

regardless of the state of the output at the time of disconnection (maximum VPWR = 16 V). A 10 k resistor needs to be added

between the MCU and each digital input pin, to ensure that the device turns off during ground disconnects and to prevent this pin

from exceeding maximum ratings.

6.3.8

Loss of Supply Lines

6.3.8.1

Loss of VDD

If the external VDD supply is disconnected (or not within specification: VDD < VDD(FAIL) with the VDD_FAIL_en bit set to a logic

[1]), all SPI register content is reset.

The outputs can still be driven by the direct inputs IN[0:3] if VPWR is within specified voltage range. The 10XSC425 uses the

battery input to power the output MOSFET-related current sense circuitry, and any other internal logic providing Fail-safe device

operation with no VDD supplied. In this state, the overtemperature, overcurrent, severe short-circuit, short to VPWR and OFF

OpenLoad circuitry, are fully operational with default values corresponding to all SPI bits. These are set to logic [0].

An unexpected Power-On Reset (

VSUPPLY(POR)) may occur at 4.8 V of VPWR. The extended battery voltage range specified from

4.0 to 28 V is reduced from 5.0 to 28 V. If the battery voltage drops below 5.0 V, the outputs will be turned off by the POR instead

of undervoltage (UV). In this case, the outputs will turn on again once the battery voltage recovers to a nominal voltage. The

counter of auto-retry will be also reset. So, it is recommended to command “off” the outputs when the battery voltage is below

5.0 V.

No current is conducted from VPWR to VDD.

6.3.8.2

Loss of VPWR

If the external VPWR supply is disconnected (or not within specification), the SPI configuration, reporting, and daisy chain features

are provided for RSTB to set to a logic [1] under VDD in nominal conditions. This fault condition can be diagnosed with a UV fault

in SPI STATR_s registers. The SPI pull-up and pull-down current sources are not operational. The previous device configuration

is maintained. No current is conducted from VDD to VPWR.

6.3.8.3

Loss of VPWR and VDD

If the external VPWR and VDD supplies are disconnected (or not within specification: (VDD and VPWR) < VSUPPLY(POR)), all SPI

register contents are reset with default values corresponding to all SPI bits set to logic [0] and all latched faults are reset.

6.3.9

EMC PERFORMANCES

All following tests are performed on a Freescale evaluation board, in accordance with the typical application schematic.

The device is protected, in case of positive and negative transients on the VPWR line (per ISO 7637-2).

The 10XSC425 successfully meets the Class 5 of the CISPR25 emission standard and 200 V/m or BCI 200 mA injection level

for immunity tests.

6.4

LOGIC COMMANDS AND REGISTERS

6.4.1

Serial Input Communication

SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15

and ending with the LSB, D0 (Table 10). Each incoming command message on the SI pin can be interpreted using the following

bit assignments: the MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bits D14:D13. The next

three bits, D12:D10, are used to select the command register. The remaining nine bits, D8:D0, are used to configure and control

the outputs and their protection features.

10XSC425 Datasheet(PDF) 40 Page - Freescale Semiconductor, Inc

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