APA150 datasheet(54/174 Pages) ACTEL

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ProASICPLUS Flash Family FPGAs

1- 50

v5.2

Predicted Global Routing Delay

Global Routing Skew

Table 1-41 • Worst-Case Commercial Conditions1

VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C

Parameter

Description

Max.

Units

Std.

–F2

tRCKH

Input Low to High3

1.1

1.3

tRCKL

Input High to Low3

1.0

1.2

tRCKH

Input Low to High4

0.8

1.0

tRCKL

Input High to Low4

0.8

1.0

Notes:

1. The timing delay difference between tile locations is less than 15ps.

2. All –F parts are only available as commercial.

3. Highly loaded row 50%.

4. Minimally loaded row.

Table 1-42 • Worst-Case Military Conditions

VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883

Parameter

Description

Max.

Units

tRCKH

Input Low to High (high loaded row of 50%)

1.1

tRCKL

Input High to Low (high loaded row of 50%)

1.0

tRCKH

Input Low to High (minimally loaded row)

0.8

tRCKL

Input High to Low (minimally loaded row)

0.8

Note: * The timing delay difference between tile locations is less than 15 ps.

Table 1-43 • Worst-Case Commercial Conditions

VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C

Parameter

Description

Max.

Units

Std.

–F*

tRCKSWH

Maximum Skew Low to High

270

320

tRCKSHH

Maximum Skew High to Low

270

320

Note: *All –F parts are only available as commercial.

Table 1-44 • Worst-Case Commercial Conditions

VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883

Parameter

Description

Max.

Units

tRCKSWH

Maximum Skew Low to High

270

tRCKSHH

Maximum Skew High to Low

270

APA150 Datasheet(PDF) 54 Page - Actel Corporation

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