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TAS5508 Datasheet(PDF) 56 Page - Texas Instruments |
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TAS5508 Datasheet(HTML) 56 Page - Texas Instruments |
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56 / 105 page  4.5 Electrical Characteristics 4.6 PWM Operation 4.7 Switching Characteristics 4.7.1 Clock Signals TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 www.ti.com Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.3-V TTL and 5 V(1) tolerant IOH = –4 mA 2.4 VOH High-level output voltage V 1.8-V LVCMOS (XTL_OUT) IOH = –0.55 mA 1.44 3.3-V TTL and 5 V(1) tolerant IOL = 4 mA 0.5 VOL Low-level output voltage V 1.8-V LVCMOS (XTL_OUT) IOL = 0.75 mA 0.5 IOZ High-impedance output current 3.3-V TTL ＝20 µA 3.3-V TTL VI = VIL ＝1 IIL Low-level input current 1.8-V LVCMOS (XTL_IN) VI = VIL ＝1 µA 5 V tolerant(2) VI = 0 V, DVDD = 3 V ＝1 3.3-V TTL VI = VIH ＝1 IIH High-level input current 1.8-V LVCMOS (XTL_IN) VI = VIH ＝1 µA 5 V tolerant(2) VI = 5.5 V, DVDD = 3 V ＝20 Fs = 48 kHz 140 Fs = 96 kHz 150 Digital supply voltage, DVDD mA Fs = 192 kHz 155 IDD Input supply current Power down 8 Normal 20 Analog supply voltage, AVDD mA Power down 2 (1) 5-V tolerant outputs are SCL and SDA. (2) 5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL. Over recommended operating conditions PARAMETER TEST CONDITIONS MODE VALUE UNIT 32-kHz data rate ＝4% 12 ＝ sample rate 384 kHz 8 ＝, 4＝, or 2＝ sample 44.1-, 88.2-, 176.4-kHz data rate ＝4% 352.8 kHz Output sample rate 1 ＝–8＝ oversampled rate 8 ＝, 4＝, or 2＝ sample 48-, 96-, 192-kHz data rate ＝4% 384 kHz rate PLL input parameters and external filter components over recommended operating conditions (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fXTALI Frequency, XTAL IN Only use 13.5-MHz crystal ≤1000 ppm 13.5 MHz fMCLKI Frequency, MCLK (1/tcyc2) 2 50 MHz MCLK duty cycle 40% 50% 60% ≥2-V MCLK = 49.152 MHz, within the min MCLK minimum high time 5 ns and max duty cycle constraints ≤0.8-V MCLK = 49.152 MHz, within the min MCLK minimum low time 5 ns and max duty cycle constraints LRCLK allowable drift before LRCLK reset 10 MCLKs External PLL filter capacitor C1 SMD 0603 Y5V 100 nF External PLL filter capacitor C2 SMD 0603 Y5V 10 nF External PLL filter resistor R SMD 0603, metal film 200 Ω (1) See the TAS5508 Example Application Schematic, Section 8. Electrical Specifications 56 Submit Documentation Feedback |
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