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TAS5508 Datasheet(PDF) 63 Page - Texas Instruments |
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TAS5508 Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 105 page  4.8.2 Left-Justified Timing 23 22 SCLK 32Clks LRCLK LeftChannel 24-BitMode 1 19 18 20-BitMode 16-BitMode 15 14 MSB LSB 32Clks RightChannel 2-ChannelLeft-JustifiedStereoInput T0034-02 4 5 9 8 1 4 5 1 0 0 0 23 22 1 19 18 15 14 MSB LSB 4 5 9 8 1 4 5 1 0 0 0 SCLK TAS5508 8-Channel Digital Audio PWM Processor www.ti.com SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 ＝ Fs is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508 masks unused trailing data bit positions. Figure 4-10. Left-Justified 64-Fs Format Submit Documentation Feedback Electrical Specifications 63 |
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