TAS5508 datasheet(79/105 Pages) TI

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7.12 Modulation Index Limit Register (0x16)

7.13 Interchannel Delay Registers (0x1B–0x22)

7.14 Channel Offset Register (0x23)

7.15 Bank-Switching Command Register (0x40)

TAS5508

8-Channel Digital Audio PWM Processor

www.ti.com

SLES091D – FEBRUARY 2004 – REVISED JULY 2009

Bits D7–D3 are Don't Care.

Table 7-12. Modulation Index Limit Register Format

LIMIT

MIN WIDTH

MODULATION

[DCLKs]

INDEX

99.2%

98.4%

97.7%

96.9%

96.1%

95.3%

94.5%

93.8%

Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, and 0x22,

respectively.

Bits D1 and D0 are Don't Care.

Table 7-13. Interchannel Delay Register Format

FUNCTION

Minimum absolute delay, 0 DCLK cycles, default for channel 1

Maximum positive delay, 31

＝ 4 DCLK cycles

Maximum negative delay, –32

＝ 4 DCLK cycles

Default value for channel 1 = –32

Default value for channel 2 = 0

Default value for channel 3 = –16

Default value for channel 4 = 16

Default value for channel 5 = –24

Default value for channel 6 = 8

Default value for channel 7 = –8

Default value for channel 8 = 24

The channel offset register is mapped into 0x23.

Table 7-14. Channel Offset Register Format

Function

Minimum absolute offset, 0 DCLK cycles, default for channel 1

Maximum absolute offset, 255 DCLK cycles

Bits D31–D24, D22–D19 are Don't Care.

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Serial-Control Interface Register Definitions

TAS5508 Datasheet(PDF) 79 Page - Texas Instruments

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