28F008B3 datasheet(18/49 Pages) INTEL

18 / 49 page

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

PRELIMINARY

When the WSM is active, bit 7 (SR.7) of the status

remaining bits in the status register indicate

whether or not the WSM was successful in

performing the desired operation (see Table 7).

3.2.3.1

Clearing the Status Register

The WSM sets status bits 1 through 7 to “1,” and

clears bits 2, 6 and 7 to “0,” but cannot clear status

bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4,

and 5 indicate various error conditions, these bits

can only be cleared by the controlling CPU through

the use of the Clear Status Register (50H)

command. By allowing the system software to

control

the

resetting

these

bits,

several

operations may be performed (such as cumulatively

programming several addresses or erasing multiple

blocks in sequence) before reading the status

series. Clear the Status Register before beginning

another command or sequence. Note, again, that

the Read Array command must be issued before

data can be read from the memory array.

3.2.4

PROGRAM MODE

Programming

executed

using

two-write

sequence. The Program Setup command (40H) is

written to the CUI followed by a second write which

specifies the address and data to be programmed.

The WSM will execute the following sequence of

internally timed events:

Program the desired bits of the addressed

memory.

Verify that the desired bits are sufficiently

programmed.

Programming of the memory results in specific bits

within an address location being changed to a “0.” If

the user attempts to program “1”s, there will be no

change of the memory cell contents and no error

occurs.

The status register indicates programming status:

while the program sequence is executing, bit 7 of

the status register is a “0.” The status register can

be polled by toggling either CE# or OE#. While

programming, the only valid commands are Read

Status Register, Program Suspend, and Program

Resume.

When programming is complete, the Program

Status bits should be checked. If the programming

operation was unsuccessful, bit SR.4 of the status

is set then VPP was not within acceptable limits, and

the WSM did not execute the program command. If

SR.1 is set, a program operation was attempted to

a locked block and the operation was aborted.

The status register should be cleared before

attempting the next operation. Any CUI instruction

can

after

programming

completed;

however, to prevent inadvertent status register

reads, be sure to reset the CUI to read array mode.

3.2.4.1

Suspending and Resuming

Program

The Program Suspend command allows program

suspension in order to read data in other locations

of memory. Once the programming process starts,

writing the Program Suspend command to the CUI

requests that the WSM suspend the program

sequence (at predetermined points in the program

algorithm). The device continues to output status

is written. Polling status register bits SR.7 and SR.2

will determine when the program operation has

been

suspended

(both

will

set

“1”).

tWHRH1/tEHRH1 specify the program suspend latency.

A Read Array command can now be written to the

CUI to read data from blocks other than that which

is suspended. The only other valid commands,

while program is suspended, are Read Status

Resume command is written to the flash memory,

the WSM will continue with the program process

and status register bits SR.2 and SR.7 will

automatically

cleared.

After

the

Program

Resume

command

written,

the

device

automatically outputs status register data when

read (see Figure 7, Program Suspend/Resume

Flowchart). VPP must remain at the same VPP level

used for program while in program suspend mode.

RP# must also remain at VIH.

3.2.4.2

VPP Supply Voltage during

Program

VPP supply voltage considerations are outlined in

Section 3.4.

28F008B3 Datasheet(PDF) 18 Page - Intel Corporation

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