28F008B3 datasheet(22/49 Pages) INTEL

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

PRELIMINARY

Start

Write 40H

Program Address/Data

Read Status Register

SR.7 = 1?

Full Status

Check if Desired

Program Complete

Read Status Register

Data (See Above)

PP Range Error

Programming Error

Attempted Program to

Locked Block - Aborted

Program Successful

SR.3 =

SR.4 =

SR.1 =

FULL STATUS CHECK PROCEDURE

Bus Operation

Write

Standby

Repeat for subsequent programming operations.

SR Full Status Check can be done after each program or after a sequence of

program operations.

Write FFH after the last program operation to reset device to read array mode.

Bus Operation

Standby

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases where multiple bytes are programmed before full status is checked.

If an error is detected, clear the status register before attempting retry or other

error recovery.

Yes

Command

Program Setup

Program

Comments

Data = 40H

Data = Data to Program

Addr = Location to Program

Check SR.7

1 = WSM Ready

0 = WSM Busy

Command

Comments

Check SR.3

1 = V

PP Low Detect

Check SR.1

1 = Attempted Program to

Locked Block - Program

Aborted

Read

Status Register Data Toggle

CE# or OE# to Update Status

Standby

Check SR.4

1 = V

PP Program Error

0605-07

Figure 6. Automated Byte Programming Flowchart

28F008B3 Datasheet(PDF) 22 Page - Intel Corporation

28F008B3 Datasheet(HTML) 22 Page - Intel Corporation

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