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28F008B3 Datasheet(PDF) 43 Page - Intel Corporation |
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28F008B3 Datasheet(HTML) 43 Page - Intel Corporation |
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43 / 49 page ![]() E SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE 43 PRELIMINARY 7.1 Reset Operations IH V IL V RP# (P) PLPH t IH V IL V RP# (P) PLPH t (A) Reset during Read Mode Abort Complete PHQV t PHWL t PHEL t PHQV t PHWL t PHEL t (B) Reset during Program or Block Erase, < PLPH t PLRH t PLRH t IH V IL V RP# (P) PLPH t Abort Complete PHQV t PHWL t PHEL t PLRH t Deep Power- Down (C) Reset Program or Block Erase, > PLPH t PLRH t 0605-17 Figure 16. AC Waveform: Deep Power-Down/Reset Operation Reset Specifications VCC = 2.7–3.6V Symbol Parameter Notes Min Max Unit tPLPH RP# Low to Reset during Read (If RP# is tied to VCC, this specification is not applicable) 1,3 100 ns tPLRH RP# Low to Reset during Block Erase or Program 2,3 22 µs NOTES: 1. If tPLPH is < 100 ns the device may still RESET but this is not guaranteed. 2. If RP# is asserted while a block erase or byte program operation is not executing, the reset will complete within 100 ns. 3. Sampled but not 100% tested. |
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