Integration principles and description

AN3165

20/31

Doc ID 17180 Rev 1

Figure 12.

Voltage management timing in integrated firmware

The dual FOC MC uses left-aligned data for the injected group while the digital PFC uses

right-aligned data for the regular group. Therefore, the converted values coming from the

code written for the digital PFC part have to be adjusted to fit the format of data used by the

dual FOC MC part.

4.2.3

Conflicts between I/O pins

As described in Section 3.3, the dual FOC MC uses a DAC for debugging purposes.

Because the DAC takes control of PA4 (DAC_OUT_1) and PA5 (DAC_OUT_2), it is not

possible to use it: the same pins are used by the digital PFC to read the PFC current and

input AC voltage.

Another conflict is generated on the PC9 pin, which represents both the TIM8_CH4 and

TIM3_CH4 signal outputs for the dual FOC MC and digital PFC respectively.

TIM3_CH4 is used to drive the power MOSFET gate, while TIM8_CH4 (or better, an edge

commutation on it) is used internally as the trigger input for the ADC3 start conversion.

Although TIM8_CH4 is used as an internal trigger for ADC3, disabling its output on the PC9

pin also disables its triggering functionality. As such, it is necessary to use another start

trigger source for the injected conversion of ADC3.

Figure 13.

Triggers for STM32 ADC3

Figure 13

shows the trigger sources for the injected conversion of ADC3. Signals from TIM1

and TIM8 are already used.

TIM4_CH3 is mapped to pins used by the dual FOC MC.

TIM5_CH4 is mapped to PA3, which is used by the digital PFC (see Table 1).