UPD178016 datasheet(37/56 Pages) NEC

37 / 56 page

µPD178004, 178006, 178016, 178018

(v) 2-wire serial I/O mode (SCK0 ... internal clock output)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCK0 cycle time

tKCY5

R = 1 k

Ω

1600

SCK0 high-level width

tKH5

C = 100 pFNote

tKCY5/2 – 160

SCK0 low-level width

tKL5

4.5 V

≤ VDD ≤ 5.5 V tKCY5/2 – 50

3.5 V

≤ VDD < 4.5 V tKCY5/2 – 100

SB0, SB1 setup time (to SCK0

↑)tSIK5

4.5 V

≤ VDD ≤ 5.5 V

300

3.5 V

≤ VDD < 4.5 V

350

400

SB0, SB1 hold time (from SCK0

↑) tKSI5

600

SB0, SB1 output delay time from

tKSO5

300

SCK0

↓

Note

R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line.

(vi) 2-wire serial I/O mode (SCK0 ... external clock input)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

SCK0 cycle time

tKCY6

1600

SCK0 high-level width

tKH6

650

SCK0 low-level width

tKL6

800

SB0, SB1 setup time (to SCK0

↑)tSIK6

100

SB0, SB1 hold time (from SCK0

↑) tKSI6

tKCY6/2

SB0, SB1 output delay time from

tKSO6

R = 1 k

Ω

4.5 V

≤ VDD ≤ 5.5 V

300

SCK0

↓

C = 100 pFNote 3.5 V

≤ VDD < 4.5 V

500

SCK0 at rising or falling edge time tR6, tF6

1000

Note

R and C are the load resistance and load capacitance of SB0 and SB1 output line.

UPD178016 Datasheet(PDF) 37 Page - NEC

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