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F20 Datasheet(PDF) 71 Page - List of Unclassifed Manufacturers

Part # F20
Description  8-ch normal DMA controllers and 8-ch dedicated DMA controllers
PDF  111 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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F20 Datasheet(HTML) 71 Page - List of Unclassifed Manufacturers

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Boxchip F20 Datasheet
Boxchip. All rights reserved.
Ver 1.01
Page 71
16.
Two Wire Interface
16.1.
TWI Controller Description
This 2-Wire Controller is designed to be used as an interface between CPU host and the
serial 2-Wire bus. It can supports all the standard 2-Wire transfer, including Slave and Master.
The communication to the 2-Wire bus is carried out on a byte-wise basis using interrupt or
polled handshaking. This 2-Wire Controller can be operated in standard mode (100K bps) or
fast-mode, supporting data rate up to 400K bps. Multiple Masters and 10-bit addressing
Mode are supported for this specified application. General Call Addressing is also supported
in Slave mode.
The 2-Wire Controller includes the following features:
Software-programmable for Slave or Master
Supports Repeated START signal
Multi-master systems supported
Allows 10-bit addressing with 2-Wire bus
Performs arbitration and clock synchronization
Own address and General Call address detection
Interrupt on address detection
Supports speeds up to 400Kbits/s (‘fast mode’)
Allows operation from a wide range of input clock frequencies
16.2.
TWI Controller Signal Description
Table 16-1. TWI Controller Signal Description
Signal
Name
Description
Type
Pin
Name
Ball#
I2C port0
TWI0_SCK
I2C-BUS Clock for Channel0
I/O
PB0
B2
TWI0_SDA
I2C-BUS Data for Channel0
I/O
PB1
A1
I2C port1
TWI1_SCK
I2C-BUS Clock for Channel1
I/O
PB18
T3
TWI1_SDA
I2C-BUS Data for Channel1
I/O
PB19
T4
I2C port2
TWI2_SCK
I2C-BUS Clock for Channel2
I/O
PB20
P1
TWI2_SDA
I2C-BUS Data for Channel2
I/O
PB21
P2



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