F20 datasheet(79/111 Pages) ETC2

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Boxchip F20 Datasheet

Ver 1.01

Page 79

21.

USB OTG Controller

21.1.

USB OTG Overview

The USB/OTG is a Dual-Role Device (DRD) controller, which supports both device and host

functions and is full compliant with the On-The-Go Supplement to the USB 2.0 Specification,

Revision 1.0a. It can also be configured as a Host-only or Device-only controller, full

compliant with the USB 2.0 Specification. It can support high-speed (HS, 480-Mbps),

full-speed (FS, 12-Mbps), and low-speed (LS, 1.5-Mbps) transfers in Host mode. It can

support high-speed (HS, 480-Mbps), and full-speed (FS, 12-Mbps) in Device mode. The

USB/OTG connects to the industry-standard AMBA High-Performance Bus (AHB) for

communication with other system modules, such as AC320 CPU, System Memory. It is fully

compliant with the AMBA Specification, Revision 2.0. As an AHB slave device,

microcontroller can access its Control and Status Registers (CSRs), the Data FIFO (DFIFO),

and queues. Industry standard Single Port RAM (SPRAM) is supported for saving area and

power. The Single Port RAM is used as Data FIFO. Standard USB transceiver can be used

through its UTMI+PHY Level2 interface. The UTMI+PHY interface is bidirectional with 8-bit

data bus. In AHB slave mode, the data transfer between the USB/OTG and the system

memory is handled by the application. For saving CPU bandwidth, USB/OTG DMA interface

can support one external DMA controller to take care of the data transfer between the

memory and USB/OTG core. The driver sets up the transfer and the USB/OTG interrupts the

CPU only on transfer completion or and error condition. One central DMA engine is designed

for the data transfer in system role. The DMA function can be disabled by software. The Host

Negotiation Protocol (HNP), Session Request Protocol (SRP), and other critical functions are

implemented in hardware for processing efficiency. The USB/OTG core also supports USB

power saving functions.

The USB2.0 OTG controller System-Level block diagram is showed below:

The USB2.0 OTG controller (SIE) includes the following features:



Complies with USB 2.0 Specification and its On-The-Go Supplement to the USB 2.0

Specification (Revision 1.0a)



Supports High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps), and Low-Speed (LS,

1.5-Mbps) in Host mode and support High-Speed (HS, 480-Mbps), Full-Speed (FS,

12-Mbps) in Device mode



Supports the Host Negotiation Protocol (HNP) and the Session Request Protocol

(SRP)



Supports the UTMI+ Level 3 interface. The 8-bit bidirectional data buses are used.



64-Byte Endpoint 0 for Control Transfer (Endpoint0)



Supports up to 4 User-Configurable Endpoints for Bulk , Isochronous, Control and

Interrupt bi-directional transfers (Endpoint1, Endpoint2, Endpoint3, Endpoint4,

Endpoint5)

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