F20 datasheet(74/111 Pages) ETC2

74 / 111 page

Boxchip F20 Datasheet

Ver 1.01

Page 74

18.

UART Interface

18.1.

UART Overview

The UART is used for serial communication with a peripheral, modem (data carrier

equipment, DCE) or data set. Data is written from a master (CPU) over the APB bus to the

UART and it is converted to serial form and transmitted to the destination device. Serial data

is also received by the UART and stored for the master (CPU) to read back.

The UART contains registers to control the character length, baud rate, parity

generation/checking, and interrupt generation. Although there is only one interrupt output

signal from the UART, there are several prioritized interrupt types that can be responsible for

its assertion. Each of the interrupt types can be separately enabled/disabled with the control

registers.

The UART has 16450 and 16550 modes of operation, which are compatible with a range of

standard software drivers. In 16550 mode, transmit and receive operations are both buffered

by FIFOs. In 16450 mode, these FIFOs are disabled.

The UART supports word lengths from five to eight bits, an optional parity bit and 1, 1 ½ or 2

stop bits, and is fully programmable by an AMBA APB CPU interface. A 16-bit programmable

baud rate generator and an 8-bit scratch register are included, together with separate

transmit and receive FIFOs. Eight modem control lines and a diagnostic loop-back mode are

provided.

Interrupts can be generated for a range of TX Buffer/FIFO, RX Buffer/FIFO, Modem Status

and Line Status conditions.

For integration in systems where Infrared SIR serial data format is required, the UART can be

configured to have a software-programmable IrDA SIR Mode. If this mode is not selected,

only the UART (RS232 standard) serial data format is available.

The UART includes the following features:



Compatible with industry-standard 16550 UARTs



64-Bytes Transmit and receive data FIFOs



DMA controller interface



Software/ Hardware Flow Control



Programmable Transmit Holding Register Empty interrupt



Support IrDA 1.0 SIR



Interrupt support for FIFOs, Status Change

18.2.

UART Controller Signal Description

Table 18-1. UART Controller Signal Description

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