GD25Q21 datasheet(17/49 Pages) ELM

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Rev.1.1

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GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash

7.6. Write Status Register (WRSR) (31H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it

can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable

(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) command (31H) has no effect on S15 and S10 of the Status Register. CS#

must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register

(WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle

(whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may

still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during

the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write

Enable Latch (WEL) is reset.

To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been

executed for the device to accept the Write Status Register Instruction. Once write enabled, the instruction is

entered by driving CS# low, sending the instruction code “31h”, and then writing the status register data byte.

To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have

been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However,

SRP1 and LB3, LB2, LB1 can not be changed from 1 to 0 because of the OTP protection for these bits. Upon

power off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will

be restored when power on again.

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,

BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined

in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register

Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect

(SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected

Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is

entered.

Figure 7. Write Status Register Sequence Diagram

Command

0 1 2 3 4 5 6 7

31H

CS#

SCLK

High-Z

8 9 10 11 12 13 14 15

MSB

Status Register in

16 17 18 19 20 21 22 23

14 13 12 11 10 9

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