GD25Q21 datasheet(15/49 Pages) ELM

15 / 49 page

Rev.1.1

49 -

http://www.elm-tech.com

GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash

7.3. Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to

change the system configuration and memory protection schemes quickly without waiting for the typical non-

volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for

Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable

for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status

Figure 4. Write Enable for Volatile Status Register Sequence Diagram

CS#

SCLK

Command(50H)

0 1 2 3 4 5 6 7

High-Z

Figure 5. Read Status Register Sequence Diagram

Command

0 1 2 3 4 5 6 7

05H or 35H

CS#

SCLK

High-Z

8 9 10 11 12 13 14 15

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB

S7~S0 or S15~S8 out

MSB

7.4. Read Status Register (RDSR) (05H or 35H)

The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read

at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles

is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to

the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will

output Status Register bits S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8.

GD25Q21 Datasheet(PDF) 15 Page - ELM Electronics