GD25Q21 datasheet(6/49 Pages) ELM

6 / 49 page

Rev.1.1

49 -

http://www.elm-tech.com

GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash

Each device has

Each block has

Each sector has

Each page has

256K

64/32K

256

bytes

256/128

pages

16/8

sectors

4/8

blocks

3. MEMORY ORGANIZATION

Block

Sector

Address range

03F000H

03FFFFH

-----

02F000H

02FFFFH

-----

020000H

020FFFH

01F000H

01FFFFH

-----

010000H

010FFFH

00F000H

00FFFFH

-----

000000H

000FFFH

GD25Q21B

GD25Q21B 64K Bytes Block Sector Architecture

4. DEVICE OPERATION

SPI Mode

Standard SPI

The GD25Q21B feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),

Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is

latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.

Dual SPI

The GD25Q21B supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast

Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two

times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional

I/O pins: IO0 and IO1.

Uniform Block Sector Architecture

GD25Q21 Datasheet(PDF) 6 Page - ELM Electronics

GD25Q21 Datasheet(HTML) 6 Page - ELM Electronics

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