GD25Q21 datasheet(28/49 Pages) ELM

28 / 49 page

Rev.1.1

49 -

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GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash

7.17. Sector Erase (SE) (20H)

The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE)

command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address

inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire

duration of the sequence.

The Sector Erase command sequence: CS# goes low → sending Sector Erase command → 3-byte address on

SI → CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit

of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon

as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector

Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.

The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase

(SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bit (see

Table1.) is not executed.

Figure 21. Sector Erase Sequence Diagram

Command

0 1 2 3 4 5 6 7

20H

CS#

SCLK

8 9

29 30 31

MSB

2 1 0

24 Bits Address

23 22

7.18. 32KB Block Erase (BE) (52H)

The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase

(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.

Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven

low for the entire duration of the sequence.

The 32KB Block Erase command sequence: CS# goes low → sending 32KB Block Erase command → 3-byte

address on SI→ CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after

the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not

executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.

While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In

Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when

it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is

reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4,

BP3, BP2, BP1, BP0) bits (see Table1.) is not executed.

Figure 22. 32KB Block Erase Sequence Diagram

Command

0 1 2 3 4 5 6 7

52H

CS#

SCLK

8 9

29 30 31

MSB

2 1 0

24 Bits Address

23 22

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