GD25Q21 datasheet(29/49 Pages) ELM

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Rev.1.1

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GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash

7.19. 64KB Block Erase (BE) (D8H)

The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase

(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.

Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven

low for the entire duration of the sequence.

The 64KB Block Erase command sequence: CS# goes low → sending 64KB Block Erase command → 3-byte

address on SI → CS# goes high. The command sequence is shown in Figure23. CS# must be driven high after

the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not

executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.

While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In

Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when

it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is

reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4,

BP3, BP2, BP1, BP0) bits (see Table1.) is not executed.

Figure 23. 64KB Block Erase Sequence Diagram

Command

0 1 2 3 4 5 6 7

D8H

CS#

SCLK

8 9

29 30 31

MSB

2 1 0

24 Bits Address

23 22

7.20. Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must

previously have been executed to set the Write Enable Latch (WEL) bit. The Chip Erase (CE) command is

entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low

for the entire duration of the sequence.

The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The

command sequence is shown in Figure24. CS# must be driven high after the eighth bit of the command code

has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-

timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status

during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle

is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if the Block

Protect (BP4,BP3,BP2, BP1, BP0) bits are set to “None protected”. The Chip Erase (CE) command is ignored if

one or more sectors are protected.

Figure 24. Chip Erase Sequence Diagram

Command

0 1 2 3 4 5 6 7

60H or C7H

CS#

SCLK

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