GD25Q21 datasheet(14/49 Pages) ELM

14 / 49 page

Rev.1.1

49 -

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GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash

7.1. Write Enable (WREN)(06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch

(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE)

and Write Status Register (WRSR), Program Security Register, Erase Security Register command. The Write

Enable (WREN) command sequence: CS# goes low → sending the Write Enable command → CS# goes high.

Command

0 1 2 3 4 5 6 7

06H

CS#

SCLK

High-Z

7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command

sequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset by

following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,

Block Erase, Chip Erase, Program Security Register, Erase Security Register commands.

Command

0 1 2 3 4 5 6 7

04H

CS#

SCLK

High-Z

Figure 2. Write Enable Sequence Diagram

Figure 3. Write Disable Sequence Diagram

GD25Q21 Datasheet(PDF) 14 Page - ELM Electronics