Z89321 datasheet(19/40 Pages) ZILOG

19 / 40 page

Z89321/371/391

Zilog

16-Bit Digital Signal Processors

DS97DSP0100

P R E L I M I N A R Y

FUNCTIONAL DESCRIPTION

Instruction Timing. Most instructions are executed in one

machine cycle. Long immediate instructions and Jump or

Call instructions are executed in two machine cycles. A

multiplication or multiplication/accumulate instruction re-

quires a single cycle. Specific instruction cycle times are

described in the Condition Code section.

Multiply/Accumulate. The multiplier can perform a 16-bit

x 16-bit multiply, or multiply accumulate, in one machine

cycle using the Accumulator and/or both the X and Y in-

puts. The multiplier produces a 32-bit result, however, only

the 24 most significant bits are saved for the next instruc-

tion or accumulation. For operations on very small num-

bers where the least significant bits are important, the data

should first be scaled by eight bits (or the multiplier and

multiplicand by four bits each) to avoid truncation errors.

Note that all inputs to the multiplier should be fractional

twoÕs-complement, 16-bit binary numbers (Figure 16). This

puts them in the range [Ð1 to 0.9999695], and the result is

in 24 bits so that the range is [Ð1 to 0.9999999]. In addition,

if 8000H is loaded into both X and Y registers, the resulting

multiplication is considered an illegal operation as an over-

flow would result. Positive one cannot be represented in

fractional notation, and the multiplier will actually yield the

result 8000H x 8000H = 8000H (Ð1 x Ð1 = Ð1).

ALU. The ALU has two input ports, one of which is con-

nected to the output of the 24-bit Accumulator. The other

input is connected to the 24-bit P-Bus, the upper 16 bits of

which are connected to the 16-bit D-Bus. A shifter between

the P-Bus and the ALU input port can shift the data by

three bits right, one bit right, one bit left or no shift (Figure

17).

Figure 16. Multiplier Block Diagram

X Register (16)

Y Register (16)

Multiplier

P Register (24)

DDATA

XDATA

MUX

Shift Unit *

* Options:

1 Bit Right

3 Bits Right

No Shift

1 Bit Left

Figure 17. ALU Block Diagram

Arithmetic Logic Unit (ALU)

Accumulator (24)

* Options:

1 Bit Right

3 Bits Right

No Shift

1 Bit Left

DDATA

MUX

Mult. (24)

Shift Unit *

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