Z89321 datasheet(22/40 Pages) ZILOG

22 / 40 page

Z89321/371/391

16-Bit Digital Signal Processors

Zilog

P R E L I M I N A R Y

DS97DSP0100

The status register can always be read in its entirety. S15-

S10 are set/reset by hardware and can only be read by

software. S9-S0 control hardware looping and can be writ-

ten by software (Table 6).

S15-S12 are set/reset by the ALU after an operation. S11-

S10 are set/reset by the user inputs. S6-S0 are control bits

described in Table 5. S7 enables interrupts. If S8 is set, the

hardware clamps at maximum positive or negative values

instead of overflowing. If S9 is set and a multiple/shift op-

tion is used, then the shifter shifts the result three bits right.

This feature allows the data to be scaled and prevents

overflows.

PC is the Program Counter. When this register is assigned

as a destination register, one NOP machine cycle is added

automatically to adjust the pipeline timing.

External Register, EXT4-EXT7, are used by the CODEC

interface and 13-bit timer, the registers are reviewed in the

CODEC interface section.

Table 6. RPL Description

Loop Size

256

128

Figure 18. Status Register

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

256

128

"Short Form Direct" bits

User Output 0-1*

Interrupt Enable

Overflow protection

MPY output arithmetically shifted

right by three bits

User Input 0-1 (Read Only)

Carry

Zero

Overflow

Negative

Ram Pointer Loop Size

* The output value is the opposite of the status register content.

S15

S14

S13

S12

S11

S10

NOV

UI1

UI0

SH3

UO1 UO0

RPL

Z89321 Datasheet(PDF) 22 Page - Zilog, Inc.

Z89321 Datasheet(HTML) 22 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL