Z89321 datasheet(34/40 Pages) ZILOG

34 / 40 page

Z89321/371/391

16-Bit Digital Signal Processors

Zilog

P R E L I M I N A R Y

DS97DSP0100

ADDRESSING MODES (Continued)

ADDRESSING MODES

This section discusses the syntax of the addressing

modes supported by the DSP assembler.

Figure 33. CODEC Timer Register

D15

D14

D13

D12

D11

D10

EXT4

Count Value (Down-Counter)

Clock Source

Count Operation

Counter

0 Oscillator/2*

1 CODEC Counter Output

0 = Disable*

1 = Enable

0 = Disable

1 = Enable*

* Default State

Table 8. Addressing Modes

Symbolic Name

Syntax

Description

<pregs>

Pn:b

Pointer Register

<dregs> (Points to RAM)

Dn:b

Data Register

X,Y,PC,SR,P , EXTn, A, BUS Hardware Registers

<accind> (Points to Program Memory

Accumulator Memory Indirect

Direct Address Expression

<limm>

#<const exp>

Long (16-bit) Immediate Value

<simm>

#<const exp>

Short (8-bit) Immediate Value

<regind> (Points to RAM)

@Pn:b

Pointer Register Indirect

@Pn:b+

Pointer Register Indirect with Increment

@Pn:bÐLOOP

Pointer Register Indirect with Loop Decrement

@Pn:b+LOOP

Pointer register Indirect with Loop Increment

<memind> (Points to Program Memory) @@Pn:b

Pointer Register Memory Indirect

@Dn:b

Data Register Memory Indirect

@@Pn:bÐLOOP

Pointer Register Memory Indirect with Loop

Decrement

@@Pn:b+LOOP

Pointer Register Memory Indirect with Loop

Increment

@@Pn:b+

Pointer Register Memory Indirect with Increment

Z89321 Datasheet(PDF) 34 Page - Zilog, Inc.

Z89321 Datasheet(HTML) 34 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL