Z89321 datasheet(21/40 Pages) ZILOG

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Z89321/371/391

Zilog

16-Bit Digital Signal Processors

DS97DSP0100

P R E L I M I N A R Y

REGISTERS

The internal registers are defined below:

The following are virtual registers as physical RAM does

not exist on the chip.

P holds the result of multiplications and is read-only.

X and Y are two 16-bit input registers for the multiplier.

These registers can be utilized as temporary registers

when the multiplier is not being used.

A is a 24-bit Accumulator. The output of the ALU is sent to

this register. When 16-bit data is transferred into this reg-

ister, it is placed into the 16 MSBs and the least significant

eight bits are set to zero. Only the upper 16 bits are trans-

ferred to the destination register when the Accumulator is

selected as a source register in transfer instructions.

Pn:b are the pointer registers for accessing data RAM, (n

= 0,1,2 refer to the pointer number) (b = 0,1 refers to RAM

Bank 0 or 1). They can be directly read from or written to,

and can point to locations in data RAM or Program Mem-

ory.

EXTn are external registers (n = 0 to 7). There are eight

16-bit registers provided here for mapping external devic-

es into the address space of the processor. Note that the

actual register RAM does not exist on the chip, but would

exist as part of the external device, such as an ADC result

latch. Use of the CODEC interface and 13-bit timer reduc-

es the number of external registers to four.

BUS is a read-only register which, when accessed, returns

the contents of the D-Bus. Bus is used for emulation only.

Dn:b refers to locations in RAM that can be used as a

pointer to locations in program memory which is efficient

for coefficient addressing. The programmer decides which

location to choose from two bits in the status register and

two bits in the operand. Thus, only the lower 16 possible

locations in RAM can be specified. At any one time, there

are eight usable pointers, four per bank, and the four point-

ers are in consecutive locations in RAM.

For example, if S3/S4 = 01 in the status register, then

D0:0/D1:0/D2:0/D3:0 refer to register locations 4/5/6/7 in

RAM Bank 0. Note that when the data pointers are being

written to, a number is actually being loaded to Data RAM,

so they can be used as a limited method for writing to

RAM.

SR is the status register, which contains the ALU status

and certain control bits (Table 5).

Output of Multiplier, 24-bit

X Multiplier Input, 16-bit

Y Multiplier Input, 16-bit

Accumulator, 24-bit

Status Register, 16-bit

Pn:b

Six Ram Address Pointers, 8-bit each

Program Counter, 16-bit

EXT4

13-Bit Timer ConÞguration Register

EXT5-1

CODEC Interface Channel 0 Data

EXT5-2

CODEC Interface Channel 0 Data

EXT6-1

CODEC Interface Channel 1 Data

EXT6-2

CODEC Interface Channel 1 Data

EXT7-1

CODEC Interface ConÞguration Register

EXT7-2

Wait-State Generator/CODEC Interface

ConÞguration Register

EXTn

External Registers, 16-bit

BUS

D-Bus

Dn:b

Eight Data Pointers*

Note: * These occupy the first four locations in RAM bank.

Table 5. Status Register Bit Functions

Status Register Bit

Function

S15 (N)

ALU Negative

S14 (OV)

ALU Overßow

S13 (Z)

ALU Zero

S12 (L)

Carry

S11 (UI1)

User Input 1

S10 (UI0)

User Input 0

S9 (SH3)

MPY Output Arithmetically

Shifted Right by Three Bits

S8 (OP)

Overßow Protection

S7 (IE)

Interrupt Enable

S6 (UO1)

User Output 1

S5 (UO0)

User Output 0

S4-S3

ÒShort Form DirectÓ bits

S2-S0 (RPL)

RAM Pointer Loop Size

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