Z89321 datasheet(24/40 Pages) ZILOG

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Z89321/371/391

16-Bit Digital Signal Processors

Zilog

P R E L I M I N A R Y

DS97DSP0100

CODEC Interface

The CODEC Interface provides direct-connect capabilities

for standard 8-, 16-bit CODECs. The interface also sup-

ports 8-bit PCM, 8-bit PCM with hardware

m-law conver-

sion (

m-law expansion is done in software), 16-bit Linear

and Crystal's Sigma-Delta Stereo CODEC modes. Regis-

ters are used to accommodate the CODEC Interface

(EXT5, EXT6 and EXT7). The CODEC interface provides

two Frame Sync signals, which allows two channels of

data for transmission/receiving.

CODEC Interface Hardware

The CODEC Interface hardware uses six 16-bit registers,

m-law compression logic and general-purpose logic to con-

trol transfers to the appropriate register (Figure 20).

CODEC Interface Control Signals

SCLK (Serial Clock)

The Serial Clock provides a clock signal for operating the

external CODEC. A 4-bit prescaler is used to determine

the frequency of the output signal.

Note: An internal divide-by-two is performed before the

clock signal is passed to the Serial Clock prescaler.

SCLK = (0.5* CLK)/PS

where: CLK = System Clock

PS = 4-bit Prescaler*

* The Prescaler is an up-counter.

Figure 20. CODEC Interface Block Diagram

m-Law

Compression

Data Bus

CLKIN

TXD

EXT5-2

CLKIN

EXT5-1

EXT6-1

EXT6-2

CONTROL

LOGIC

RXD

EXT7-1

EXT7-2

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