Z89321 datasheet(25/40 Pages) ZILOG

25 / 40 page

Z89321/371/391

Zilog

16-Bit Digital Signal Processors

DS97DSP0100

P R E L I M I N A R Y

TXD (Serial Output to CODEC)

The TXD line provides 8-, 16-, and 64-bit data transfers.

Each bit is clocked out of the processor by the rising edge

of the SCLK, with the MSB transmitted first.

RXD (Serial Input from CODEC)

The RXD line provides 8-, 16-, and 64-bit data transfers.

Each bit is clocked into the processor by the falling edge of

the SCLK, with the MSB received first.

FS0, FS1 (Frame Sync)

The Frame Sync is used for enabling data transfer/receive.

The rising and falling edge of the Frame Sync encloses the

serial data transmission.

Interrupt

Once the transmission of serial data is completed an inter-

nal interrupt signal is initiated. A single-cycle Low pulse al-

lows an interrupt on INT1. When this occurs, the processor

will jump to the defined Interrupt 1 vector location (Figure

21).

CODEC INTERFACE TIMING

Figure 21 depicts a typical 8-bit serial data transfer using

both of the CODEC Interface Channels. The transmitting

data is clocked out on the rising edge of the SCLK signal.

An external CODEC clocks data in on the falling edge of

the SCLK signal. Once the serial data is transmitted, an in-

terrupt is given. The CODEC interface signals are not initi-

ated if the CODEC interface is not enabled.

The following modes are available for FSYNC and SCLK

signals:

The CODEC interface timing is independent of the proces-

sor clock when external mode is chosen. This feature pro-

vides the capability for an external device to control the

transfer of data to the Z89321. The Frame Sync signal en-

velopes the transmitted data, therefore care must be taken

to ensure proper sync signal timing (Figure 21).

Full Duplex Operation

The Transmit and Receive lines are used for transfer of se-

rial data to or from the CODEC interface. The CODEC in-

terface performs both data transmit and receive simulta-

neously.

Control Registers

The CODEC interface is double-buffered, therefore, four

registers are provided for CODEC interface data storage.

EXT5-1 and EXT5-2 operate with the Frame Sync 0 while

EXT6-1 and EXT6-2 operate with Frame Sync 1. In 8- or

16-bit mode, the CODEC interface uses EXT5-1 and

EXT6-1. For Stereo mode, all four registers are used (Fig-

ures 22 and 23).

The CODEC Interface Control Register (EXT7-1) is shown

in Figure 14. Setting of the CODEC mode, FSYNC, and

Enable/Disable of CODEC 0 is done through this register.

The Wait-State Generator, SCLK, and CODEC 1 are con-

trolled from EXT7-2 (Figure 24).

Figure 21. CODEC Interface Timing (8-Bit Mode)

int1_

fs1

sclk

fs0

txd

rxd

SCLK

FSYNC

Internal

External

Internal

External

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