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Z89321 Datasheet(PDF) 28 Page - Zilog, Inc. |
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Z89321 Datasheet(HTML) 28 Page - Zilog, Inc. |
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28 / 40 page ![]() Z89321/371/391 16-Bit Digital Signal Processors Zilog 28 P R E L I M I N A R Y DS97DSP0100 Figure 25. WSG, SCLK and CODEC Interface Control Register D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 EXT7-2 Wait State EXT0 Wait State EXT1 Wait State EXT2 Wait State EXT3 Wait State EXT4 Wait State EXT5 Wait State EXT6 SCLK 0 External Source* 1 Internal Source CODEC 1 Disable/Enable 0 = Disable* 1 = Enable nws - no wait states ws - one wait states 00 no wait states (nws) 01 read (nws), write (ws) 10 read (ws), write (nws) 11 read (ws), write (ws) *Default |
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