Analog Integrated Circuit Device Data

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21

Freescale Semiconductor

BC3770

5.3.10.3 Battery Remote Sensing

BATSNSN pins are used. In the real application, there may be some voltage drop between the CHGOUT pin and the + terminal, which

comes from parasitic resistance, due to the PCB trace and a charge current. This voltage drop makes the VBAT_REG not regulate at the

target regulation voltage. To reduce the charging time, place those two pins, BATREG and BATSNSN, as close to each + and - terminal

on the battery pack as possible.

5.3.10.4 Adaptive-Input Current Limit (AICL)

then the VBUS supply will collapse and the device won't function properly under these conditions. To keep the device functional with a

current and voltage limited VBUS source, the device in Start-up mode automatically starts incrementing the input current limit to either the

default or pre-programmed value until either the input current limit is detected or the VBUS voltage detects the AICL threshold, to keep

input supply voltage as a valid power source to provide the load for the application. The device allows the maximum current the input

supply can possibly provide without severely collapsing.

In general, the AICL function is enabled whenever the input current tries to exceed the input current limit, while charging the battery and/

or providing the system load. At the beginning of the charge cycle with discharged battery, the required input current could be lower than

the VBUS current limit. The input current increases as the battery voltage increases. Eventually, the input current may exceed the VBUS

input current limit. If this happens, the AICL function takes over and lowers the charge current below the programmed value to keep VBUS

around VAICL_TH.

Most of the time charge reduction occurs at the beginning of charge cycle when a low current limited AC adapter or USB port is connected

as a valid input source. During start-up the device detects the current limited supply by slowly stepping up the input current with a

programmable soft-start clock period. Each current step is around 25 mA. As the charge and system current are stepped up, the input

this happens, the device steps down the input current by 25 mA at the next clock rising edge. This allows the input supply voltage to rise

be exceed. The input reduction continues to step up and down the input current by 25 mA to maintain the input supply voltage as close

Figure 11. AICL Operation

V

AIC L_TH

I

IN_LIM

VBUSIN

OTP-Programmable

Soft Start Clock Period

25mA